Booth Multiplication Calculator
Multiply signed two’s-complement binary integers using Booth’s algorithm. Follow Q0 and Q-1 decisions, accumulator operations, arithmetic right shifts and every register state through the final signed binary product.
| Cycle | Q0 Q-1 | Operation | A Before Shift | Q Before Shift | A After Shift | Q After Shift | New Q-1 |
|---|---|---|---|---|---|---|---|
| Enter values and calculate to view the Booth cycles. | |||||||
What Is Booth Multiplication?
Booth multiplication is an algorithm for multiplying signed binary integers represented in two’s complement. Instead of processing only the current multiplier bit, Booth’s method examines the current least significant multiplier bit Q0 together with an additional previous-bit value called Q-1.
The Q0 and Q-1 pair determines whether the multiplicand should be added to the accumulator, subtracted from the accumulator or whether no arithmetic operation is required.
After each decision, the combined accumulator, multiplier and Q-1 state undergoes an arithmetic right shift. The process repeats once for every multiplier bit.
Booth Algorithm Decision Table
| Q0 | Q-1 | Accumulator Operation | Next Action |
|---|---|---|---|
| 0 | 0 | No operation | Arithmetic right shift |
| 0 | 1 | A = A + M | Arithmetic right shift |
| 1 | 0 | A = A – M | Arithmetic right shift |
| 1 | 1 | No operation | Arithmetic right shift |
Registers Used in Booth’s Algorithm
M — Multiplicand
M stores the signed two’s-complement multiplicand throughout the multiplication process.
A — Accumulator
The accumulator starts at zero and temporarily stores additions and subtractions involving M.
Q — Multiplier
Q initially contains the multiplier. Its least significant bit Q0 is examined during every Booth cycle.
Q-1 — Previous Bit
Q-1 begins at zero and receives the previous least significant bit of Q after each shift.
Booth Multiplication Steps
A = 0
M = multiplicand
Q = multiplier
Q-1 = 0
Inspect Q0 Q-1:
01 → A = A + M
10 → A = A – M
00 → No arithmetic operation
11 → No arithmetic operation
Perform an arithmetic right shift.
Repeat once for every multiplier bit.
Final product:
A concatenated with Q
Arithmetic Right Shift in Booth Multiplication
An arithmetic right shift differs from a logical right shift because it preserves the sign of a two’s-complement value.
During a Booth shift, the most significant bit of accumulator A is retained. A’s least significant bit enters the most significant position of Q, and Q’s least significant bit becomes the new Q-1.
A = 1101
Q = 0110
Q-1 = 0
The sign of A is preserved during the shift because A begins with 1.
Worked Example: 3 × -2
0011 = 3
4-bit Q:
1110 = -2
Decimal:
3 × -2 = -6
8-bit two’s-complement product:
11111010
Worked Example: -3 × -2
Q = 1110 = -2
-3 × -2 = 6
8-bit product:
00000110
Worked Example: 5 × 3
Q = 0011 = 3
5 × 3 = 15
8-bit product:
00001111
Signed Range by Bit Width
| Width | Minimum | Maximum | Product Width |
|---|---|---|---|
| 4 bits | -8 | 7 | 8 bits |
| 6 bits | -32 | 31 | 12 bits |
| 8 bits | -128 | 127 | 16 bits |
Booth Multiplication and Two’s Complement
Booth’s algorithm works naturally with two’s-complement signed integers. The most significant input bit acts as the sign bit, allowing positive and negative values to participate in the same multiplication procedure.
| 4-Bit Binary | Signed Decimal |
|---|---|
| 0000 | 0 |
| 0011 | 3 |
| 0111 | 7 |
| 1111 | -1 |
| 1110 | -2 |
| 1101 | -3 |
| 1000 | -8 |
Why Booth’s Algorithm Is Useful
Signed Multiplication
Positive and negative two’s-complement operands can be processed using the same algorithm.
Runs of Multiplier Ones
Booth recoding can reduce repeated addition behavior when the multiplier contains consecutive groups of 1 bits.
Digital Logic Study
The method demonstrates how registers, arithmetic operations and shifts can combine to perform multiplication.
Computer Architecture
Booth encoding is an important concept in the study and design of signed multiplier hardware.
Booth Multiplication vs Basic Binary Multiplication
| Feature | Basic Binary Multiplication | Booth Multiplication |
|---|---|---|
| Signed operands | Needs sign handling | Designed for two’s complement |
| Multiplier decision | Current multiplier bit | Q0 and Q-1 |
| Operations | Mainly addition | Addition and subtraction |
| Shift behavior | Implementation dependent | Arithmetic right shift |
| Final output | Binary product | Signed two’s-complement product |
Important Booth Multiplication Notes
The leading bit therefore acts as the sign bit.
For n-bit operands, the valid signed range is from -2^(n-1) through 2^(n-1)-1.
The result uses twice the input width.
The arithmetic right shift must preserve the accumulator sign. A logical right shift would not correctly model signed Booth multiplication.