Cache Address Breakdown Calculator
Break a binary or hexadecimal memory address into cache tag, set index and block offset fields. Enter the address width, total cache size, block size and associativity to calculate the exact cache address layout.
Offset Bits = log2(Block Size)
Set Bits = log2(Sets)
Tag Bits = Address Width – Set Bits – Offset Bits
What Is Cache Address Breakdown?
A cache address breakdown divides a memory address into fields used by a CPU cache. In a conventional set-associative cache, those fields are the tag, set index and block offset.
The block offset identifies a byte inside one cache block. The set index identifies which cache set is checked. The tag distinguishes different memory blocks that can map to the same set.
Cache Address Field Layout
A typical byte-addressable cache address is organized as:
The exact number of bits assigned to each field depends on address width, cache capacity, block size and associativity.
Cache Address Breakdown Formula
For a set-associative cache, first determine the number of sets:
Then calculate:
Set Index Bits = log2(Number of Sets)
Tag Bits = Address Width – Set Index Bits – Block Offset Bits
Cache Address Example
Suppose a system uses a 16-bit address, a 1 KB cache, 16-byte blocks and 2-way associativity.
Block Size: 16 bytes
Associativity: 2
The number of sets is:
Therefore:
Set Bits = log2(32) = 5
Tag Bits = 16 – 5 – 4 = 7
What Are Block Offset Bits?
The block offset identifies a specific byte inside a cache block. If each block contains 16 bytes, four bits are required because 2^4 equals 16.
These are the lowest-order bits of the memory address in a byte-addressable cache.
What Are Set Index Bits?
The set index selects one cache set. If the cache contains 32 sets, five binary bits are required to identify values from 0 through 31.
Set index bits: 5
What Are Cache Tag Bits?
The tag consists of the remaining higher-order address bits after the set index and block offset bits have been assigned.
Set: 5 bits
Offset: 4 bits
Tag: 16 – 5 – 4 = 7 bits
The cache compares the stored tag in a candidate line with the tag portion of the requested memory address.
Direct-Mapped Cache Address Breakdown
A direct-mapped cache has associativity equal to one. Every memory block maps to exactly one cache line and therefore one set.
In a direct-mapped cache:
The same tag, set and offset decomposition rules still apply.
2-Way Set-Associative Cache
In a two-way set-associative cache, every set contains two cache lines. A memory block maps to one set but may be placed in either of its two ways.
Block: 16 bytes
Ways: 2
Lines: 1024 / 16 = 64
Sets: 64 / 2 = 32
4-Way Set-Associative Cache
Increasing associativity decreases the number of sets for a fixed total cache size and block size.
Block: 64 bytes
Ways: 4
Total lines: 4096 / 64 = 64
Sets: 64 / 4 = 16
Four set-index bits are needed because 16 equals 2^4.
Cache Size vs Number of Cache Lines
The number of physical cache lines is calculated as:
Associativity does not change the total number of lines when total cache capacity and block size remain constant. Instead, it changes how those lines are grouped into sets.
Cache Block Size and Offset Bits
| Block Size | Offset Bits |
|---|---|
| 4 bytes | 2 bits |
| 8 bytes | 3 bits |
| 16 bytes | 4 bits |
| 32 bytes | 5 bits |
| 64 bytes | 6 bits |
| 128 bytes | 7 bits |
Cache Set Index Example
If a cache contains 64 sets:
Therefore six address bits are needed for the set index.
Those six bits can represent set numbers from decimal 0 through 63.
How a Memory Address Maps to a Cache Set
After removing the low-order block offset bits, the next set-index bits determine which cache set the requested memory block maps to.
Different addresses can contain different tags while sharing the same set-index field. Those addresses compete for lines within that set.
Why Tag Bits Are Needed
A cache is much smaller than the full address space. Many different main-memory blocks therefore map to the same cache set.
The tag records which memory block is currently stored in a cache line. A tag comparison is therefore required to distinguish different blocks that share a set index.
32-Bit Cache Address Example
Suppose a 32-bit system uses a 32 KB cache, 64-byte blocks and 8-way associativity.
Blocks: 32768 / 64 = 512 lines
Sets: 512 / 8 = 64
Then:
Set Bits: log2(64) = 6
Tag Bits: 32 – 6 – 6 = 20
The 32-bit address layout is therefore:
Cache Address Breakdown vs Memory Address Calculator
These tools perform different stages of memory analysis.
| Tool | Main Task |
|---|---|
| Binary Memory Address Calculator | Calculate an address using base + offset |
| Cache Address Breakdown Calculator | Split an existing address into cache fields |
The cache calculator therefore expects the memory address to already be known.
Cache Address Breakdown vs Memory Map
A cache breakdown analyzes the bit fields of one address under a cache configuration. A memory map instead describes larger regions of an address space.
Memory Map: Region start + region size + region end
Those are different calculations and should remain separate.
Why Power-of-Two Values Matter
Standard binary cache indexing assumes block sizes and set counts that are powers of two. This makes each field correspond to an exact number of binary address bits.
For example, 16 bytes requires four bits and 64 sets requires six bits. A non-power-of-two configuration cannot be represented by a simple fixed binary field split in the same way.
Cache Address Breakdown in Computer Architecture
Tag, index and offset calculations are widely used when studying CPU caches, memory hierarchy, processor architecture and low-level performance.
They are also useful when analyzing cache conflicts, understanding direct-mapped versus set-associative caches and working through computer-architecture exercises.
Important Cache Address Breakdown Notes
The entered hexadecimal memory address must fit within the selected address width.
Total cache size must be divisible by block size × associativity.
Block size must be a power of two.
The resulting number of cache sets must also be a power of two.
Block offset bits equal log2(block size).
Set index bits equal log2(number of sets).
Tag bits are the remaining high-order address bits.
The tool supports direct-mapped caches by selecting 1-way associativity.
This calculator does not simulate cache hits or misses, replacement policies, write policies, multi-level caches, virtual addressing or TLB behavior.
For a real CPU, verify cache geometry and addressing details from the processor documentation.