UART Frame Calculator
Build a UART serial frame from a data value and framing configuration. Calculate the start bit, LSB-first data sequence, optional parity bit, stop bits and complete transmitted binary frame.
What Is a UART Frame?
UART, or Universal Asynchronous Receiver/Transmitter, transfers serial data without a shared clock signal. Instead, the transmitter and receiver agree on framing settings such as the number of data bits, parity and stop bits.
Each transmitted data unit is surrounded by framing bits so the receiver can determine where the serial data begins and ends.
UART Frame Structure
A basic UART frame normally contains a start bit, several data bits and one or more stop bits. A parity bit may optionally appear between the data and stop fields.
The UART line is normally idle at logic 1. A logic-0 start bit signals the beginning of a new frame.
UART Data Is Sent LSB First
UART commonly transmits the least-significant data bit first.
For example, hexadecimal 55 is:
Normal binary display: 01010101
Bit 0 is already the rightmost bit in normal binary notation, so the transmitted data sequence is produced by sending bit 0 first, followed by bit 1 and continuing toward the most-significant data bit.
UART Start Bit
The start bit is normally logic 0 and occupies one bit period. The transition from the idle-high state to the start bit allows the receiving UART to synchronize its sampling with the incoming character.
Start: 0
UART Parity Bit
Parity provides a simple error-detection mechanism. The parity bit is calculated from the number of 1 bits in the transmitted data field.
| Parity | Rule |
|---|---|
| None | No parity bit is transmitted |
| Even | Total number of 1s including parity is even |
| Odd | Total number of 1s including parity is odd |
Even Parity Example
Suppose an eight-bit data value contains three logic-1 bits.
Even parity requires total 1-count: Even
Parity bit: 1
Final 1-count: 4
If the data already contains an even number of ones, the even parity bit is 0.
Odd Parity Example
Odd parity works in the opposite direction. The parity bit is selected so the total count of 1 bits becomes odd.
Odd parity requires: Odd number of 1s
Parity bit: 1
Final 1-count: 5
UART Stop Bits
Stop bits are transmitted as logic 1 and indicate the end of a frame. This calculator supports one or two complete stop bits.
2 stop bits: 11
UART 8N1 Frame
One of the most common UART configurations is written as 8N1.
N = No parity
1 = 1 stop bit
The complete frame therefore contains:
Total: 10 bits
UART 8E1 Frame
An 8E1 configuration uses eight data bits, even parity and one stop bit.
Data: 8 bits
Parity: 1 bit
Stop: 1 bit
Total: 11 bits
UART Frame Overhead
Not every bit in a UART frame contains payload data. Start, parity and stop bits are framing overhead.
Payload: 8 bits
Frame: 10 bits
Overhead: 2 bits
The payload efficiency is the percentage of total transmitted frame bits that belong to the data field.
Common UART Frame Formats
| Format | Data Bits | Parity | Stop Bits | Total Bits |
|---|---|---|---|---|
| 8N1 | 8 | None | 1 | 10 |
| 8N2 | 8 | None | 2 | 11 |
| 8E1 | 8 | Even | 1 | 11 |
| 8O1 | 8 | Odd | 1 | 11 |
| 7E1 | 7 | Even | 1 | 10 |
Where UART Frames Are Used
UART serial communication is widely used in microcontrollers, embedded devices, development boards, sensors, GPS receivers, Bluetooth modules, industrial controllers, debugging ports and many other electronic systems.
Understanding the exact frame bits can be useful when debugging logic-analyzer captures or checking whether transmitter and receiver framing settings agree.
Important UART Frame Notes
The start bit is assumed to be logic 0.
Data is transmitted least-significant bit first.
The calculator supports 5 through 9 data bits.
Parity can be None, Even or Odd.
Stop bits are represented as logic 1.
The tool supports one or two stop bits.
The data value must fit within the selected number of data bits.
This calculator does not calculate baud rate or transmission time.
Actual UART hardware may support additional framing modes such as mark parity, space parity or fractional stop-bit configurations.