RISC-V Machine Instruction Utility

RISC-V Instruction Encoder & Decoder

Encode common 32-bit RISC-V assembly instructions into hexadecimal and binary machine code, or decode a 32-bit instruction word into mnemonic, instruction format, opcode, register fields, funct3, funct7 and immediate values.

✓ RV32I ✓ RV64I Base Forms ✓ R / I / S ✓ B / U / J ✓ ABI Register Names

RV32

Encode / Decode Instruction

● Ready

RISC-V Assembly Instruction Examples: add x5,x6,x7 · addi a0,a1,10 · lw a0,8(sp) · beq x1,x2,16

Architecture Width RV64 mode also allows LD, LWU and SD plus 6-bit shift amounts.

32-Bit Instruction Enter hexadecimal, binary or decimal 32-bit instruction data.

Input Format

Decoder scope: this tool focuses on common 32-bit base integer RISC-V instruction encodings. It does not treat a 16-bit compressed instruction, floating-point instruction, vector instruction or unknown extension opcode as though it were standard RV32I.

RISC-V Instruction Result Calculated

Instruction —

Machine Code Hex —

Unsigned Decimal —

Instruction Format —

Opcode —

rd —

rs1 —

rs2 —

Immediate —

funct3 —

funct7 —

Little-Endian Bytes —

Architecture —

32-Bit Instruction Binary —

Field	Bits	Binary	Decimal	Meaning

Instruction Encoding / Decoding Breakdown —

What Is a RISC-V Instruction Encoder & Decoder?

A RISC-V instruction encoder converts an assembly instruction into the bit fields stored in machine code. A decoder performs the reverse operation by reading the opcode and associated register, function and immediate fields from a 32-bit instruction word.

Most base RISC-V integer instructions use one of six commonly discussed formats: R, I, S, B, U or J.

RISC-V 32-Bit Instruction Layout

A normal uncompressed RISC-V instruction is 32 bits wide. The lowest seven bits contain the major opcode.

Bits 6..0
= Opcode

The remaining fields depend on the instruction format.

R-Type Instruction Format

31       25 24    20 19    15 14 12 11     7 6       0
+-----------+--------+--------+-----+---------+---------+
|  funct7   |  rs2   |  rs1   | f3  |   rd    | opcode  |
+-----------+--------+--------+-----+---------+---------+

R-type instructions include register-to-register arithmetic and logical operations such as ADD, SUB, AND, OR, XOR and shifts.

ADD Instruction Example

add x5, x6, x7

rd  = x5
rs1 = x6
rs2 = x7

funct7 = 0000000
funct3 = 000
opcode = 0110011

The tool combines these fields into one 32-bit instruction word and also shows the corresponding little-endian byte sequence.

SUB vs ADD Encoding

ADD and SUB use the same opcode, destination register, source register positions and funct3 value. The important distinction is funct7.

ADD funct7:
0000000

SUB funct7:
0100000

I-Type Instruction Format

31               20 19    15 14 12 11     7 6       0
+-------------------+--------+-----+---------+---------+
|   immediate[11:0] |  rs1   | f3  |   rd    | opcode  |
+-------------------+--------+-----+---------+---------+

I-type encoding is used by immediate arithmetic, loads, JALR and several other instruction families.

ADDI Example

addi a0, a1, 10

a0 = x10
a1 = x11

rd  = 10
rs1 = 11
imm = 10

opcode:
0010011

Signed 12-bit immediates normally range from -2048 through 2047 for the ordinary I-type immediate operations.

Load Instructions

Load instructions use an I-type encoding and commonly use assembly syntax such as:

lw a0, 8(sp)

rd     = a0
rs1    = sp
offset = 8

RV32I includes LB, LH, LW, LBU and LHU. RV64I additionally provides forms such as LD and LWU.

S-Type Store Format

Store instructions divide the 12-bit immediate between two regions of the instruction word.

sw a0, 12(sp)

rs2 = a0
rs1 = sp
imm = 12

The upper immediate bits occupy bits 31–25 while the lower five immediate bits occupy bits 11–7.

B-Type Branch Format

Conditional branch instructions use a rearranged immediate because branch targets are encoded as signed PC-relative offsets with bit zero implied to be zero.

beq x1, x2, 16

rs1 = x1
rs2 = x2
offset = +16 bytes

A branch offset must therefore be aligned to two bytes.

Common RISC-V Branch Instructions

Mnemonic	Condition
BEQ	Branch if equal
BNE	Branch if not equal
BLT	Signed less than
BGE	Signed greater than or equal
BLTU	Unsigned less than
BGEU	Unsigned greater than or equal

U-Type Instructions

LUI and AUIPC use U-type encoding. Their 20-bit immediate occupies bits 31 through 12 directly.

lui x5, 0x12345

Immediate field:
0x12345

Encoded upper bits:
0x12345000

J-Type JAL Instruction

JAL stores a return address in rd and uses a signed PC-relative jump offset. The immediate bits are rearranged across the instruction word.

jal ra, 32

rd = ra = x1

Jump offset:
+32 bytes

As with branch offsets, JAL targets are encoded with an implied zero low bit.

JALR Instruction

JALR uses the I-type format and calculates its target from a source register plus a signed 12-bit immediate.

jalr ra, 0(sp)

The calculator accepts the familiar offset(base-register) form.

RISC-V Register Numbers and ABI Names

Register	ABI Name	Common Role
x0	zero	Constant zero
x1	ra	Return address
x2	sp	Stack pointer
x5–x7	t0–t2	Temporary registers
x8	s0 / fp	Saved register / frame pointer
x10–x17	a0–a7	Arguments / return values
x18–x27	s2–s11	Saved registers
x28–x31	t3–t6	Temporary registers

The encoder accepts both numerical register names and common ABI aliases.

RISC-V Instruction Endianness

The instruction value is commonly written as one 32-bit hexadecimal word. On a little-endian RISC-V system, the bytes appear in memory from least significant byte to most significant byte.

Instruction word:
0x007302B3

Little-endian bytes:
B3 02 73 00

RV32I vs RV64I

Both RV32I and RV64I use many of the same 32-bit instruction encodings. However, RV64I adds operations for 64-bit loads and stores and permits a six-bit shift amount for XLEN-sized immediate shifts.

Selecting RV64I does not turn this page into a decoder for every RV64 extension. It changes only the supported base-integer forms implemented by this calculator.

Supported Instructions

Family	Supported Examples
R-Type	ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND
I Arithmetic	ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI
Loads	LB, LH, LW, LBU, LHU, LD, LWU
Stores	SB, SH, SW, SD
Branches	BEQ, BNE, BLT, BGE, BLTU, BGEU
Upper	LUI, AUIPC
Jump	JAL, JALR
System	ECALL, EBREAK

RISC-V Encoder & Decoder FAQs

How many bits is a normal RISC-V instruction?

A standard uncompressed base instruction is commonly 32 bits wide.

What is the RISC-V opcode width?

The major opcode occupies the lowest seven bits of a 32-bit base instruction.

What is an R-type instruction?

R-type instructions use rd, rs1 and rs2 register fields together with funct3, funct7 and the opcode.

What is an I-type instruction?

I-type instructions contain rd, rs1, funct3, opcode and a 12-bit immediate field.

What is the ADD opcode in RISC-V?

Base integer register-register ADD uses major opcode binary 0110011, hexadecimal 0x33.

How are ADD and SUB distinguished?

They use the same major opcode and funct3, but different funct7 values.

What is x0 in RISC-V?

x0, also called zero, always reads as zero and discards writes.

What register is ra?

The ABI alias ra refers to x1, the return-address register.

What register is sp?

sp is the ABI alias for x2, the stack pointer.

Can I use a0 instead of x10?

Yes. The encoder accepts standard ABI aliases such as a0, a1, sp, ra and t0.

Does this decode compressed RISC-V instructions?

No. This tool expects one 32-bit instruction word and does not decode the optional 16-bit compressed instruction extension.

Does this support floating-point instructions?

No. The current tool is focused on common base integer instruction formats.

Are branch offsets byte offsets?

Yes. The assembly input uses the signed byte displacement, while the encoded instruction rearranges the immediate bits and implies a zero low bit.

What is the immediate range for ADDI?

The ordinary ADDI immediate is a signed 12-bit value from -2048 through 2047.

How are RISC-V instructions stored on little-endian systems?

The least-significant byte of the 32-bit instruction word appears at the lowest memory address.

Encode and Decode RISC-V Machine Instructions

Convert common RV32I and RV64I assembly forms into exact 32-bit instruction words, or inspect machine code field-by-field without manually rearranging RISC-V immediate and register bits.