ARM A32 Machine Code Utility

ARM Instruction Decoder

Decode a 32-bit ARM A32 instruction into assembly-style output and inspect its condition code, instruction class, opcode, registers, immediate values, addressing bits and PC-relative branch displacement.

✓ Data Processing ✓ LDR / STR ✓ B / BL ✓ BX ✓ LDM / STM

A32

Decode ARM Machine Instruction

● Ready

32-Bit ARM Instruction Enter one ARM/A32 instruction as hexadecimal, binary or unsigned decimal.

Input Format Little-endian mode accepts four bytes such as 01 00 80 E0.

Scope: this decoder is for classic 32-bit ARM/A32 instruction words. Thumb, Thumb-2/T32 and AArch64/A64 use different encodings. Unknown or extension patterns are reported conservatively rather than assigned an invented instruction name.

ARM Instruction Decode Result Decoded

Decoded A32 Instruction —

Hex Word —

Unsigned Decimal —

Instruction Class —

Condition —

Opcode / Operation —

Rd —

Rn —

Rm / Rs —

Immediate / Offset —

S Bit —

Little-Endian Bytes —

Instruction Width 32-bit A32

32-Bit Instruction Binary —

Field	Bits	Binary / Value	Decimal	Meaning

Bit-Level Decode Breakdown —

What Is an ARM Instruction Decoder?

An ARM Instruction Decoder converts a binary or hexadecimal machine instruction into its constituent A32 fields. Depending on the instruction class, those fields can include a condition code, operation code, destination and source registers, immediate values, shift information, memory addressing flags or branch displacement.

This page focuses on classic 32-bit ARM instruction encoding, commonly called A32.

ARM A32 Instruction Width

A normal A32 instruction occupies exactly 32 bits. Unlike Thumb instruction sets, the decoder can therefore treat every supplied value as one complete four-byte instruction word.

32 bits
= 4 bytes
= 8 hexadecimal digits

ARM Condition Code Bits

For many A32 instructions, bits 31 through 28 contain a four-bit condition field.

Bits	Suffix	Meaning
0000	EQ	Equal
0001	NE	Not equal
0010	CS / HS	Carry set / unsigned higher or same
0011	CC / LO	Carry clear / unsigned lower
0100	MI	Minus / negative
0101	PL	Plus / positive or zero
0110	VS	Overflow
0111	VC	No overflow
1000	HI	Unsigned higher
1001	LS	Unsigned lower or same
1010	GE	Signed greater than or equal
1011	LT	Signed less than
1100	GT	Signed greater than
1101	LE	Signed less than or equal
1110	AL	Always

ARM Data Processing Instructions

Many familiar arithmetic and logical A32 instructions use the data-processing format. Examples include ADD, SUB, MOV, CMP, AND, ORR and EOR.

cond | 00 | I | opcode | S | Rn | Rd | Operand2

Operand2 can represent either a rotated immediate constant or a register with an optional shift.

ARM Data Processing Opcodes

Opcode	Mnemonic
0000	AND
0001	EOR
0010	SUB
0011	RSB
0100	ADD
0101	ADC
0110	SBC
0111	RSC
1000	TST
1001	TEQ
1010	CMP
1011	CMN
1100	ORR
1101	MOV
1110	BIC
1111	MVN

Example: ADD r0, r0, r1

Machine code:
0xE0800001

Condition:
1110 → AL

Opcode:
0100 → ADD

Rn:
r0

Rd:
r0

Operand2:
r1

Decoded:
ADD r0, r0, r1

Immediate ARM Constants

Classic A32 data-processing immediate values are not simply arbitrary 12-bit integers. Operand2 contains an eight-bit immediate value and a four-bit rotate field.

Immediate =
ROR(imm8, 2 × rotate)

The decoder performs this rotation and shows the resulting constant.

Example: MOV r0, #1

Instruction:
0xE3A00001

Opcode:
MOV

Rd:
r0

Immediate:
#1

ARM LDR and STR Instructions

Single data-transfer instructions use a separate format containing load/store, byte/word, pre/post indexing, add/subtract offset and writeback control bits.

01 I P U B W L Rn Rd Offset12

When L is set the instruction is a load. When L is clear it is a store.

Example: LDR r0, [r1, #4]

Instruction:
0xE5910004

L = 1
→ Load

Rn = r1
Rd = r0

Offset:
4

Decoded:
LDR r0, [r1, #4]

ARM Branch Instructions

A32 B and BL instructions contain a signed 24-bit displacement. The encoded value is shifted left by two bits before being added to the architectural PC value.

Branch displacement =
SignExtend(imm24 << 2)

The tool reports the PC-relative displacement. Without the runtime address of the instruction, an absolute destination address cannot be calculated safely.

ARM PC and Branch Offsets

For classic A32 branch calculations, the architectural PC used by the branch calculation corresponds to the current instruction address plus eight bytes.

Because this tool receives only the machine instruction and not its memory address, it reports a displacement relative to the A32 PC rather than inventing an absolute branch target.

B vs BL

The Link bit distinguishes the normal branch instruction from Branch with Link. BL records a return address in the link register.

L = 0
→ B

L = 1
→ BL

BX Instruction

BX branches to an address held in a register. It is commonly seen when returning through the link register or switching instruction state according to the target address.

0xE12FFF1E

Rm = r14 / lr

Decoded:
BX lr

ARM Register Names

Register	Common Alias
r0–r12	General-purpose registers
r13	sp — Stack Pointer
r14	lr — Link Register
r15	pc — Program Counter

Little-Endian ARM Instruction Bytes

The hexadecimal instruction word is normally written most-significant digit first, but ARM systems frequently store A32 instructions in little-endian byte order.

Instruction:
0xE0800001

Little-endian bytes:
01 00 80 E0

The decoder accepts either representation when the appropriate input mode is selected.

ARM Multiply Instructions

Classic MUL and MLA instructions use a recognizable encoding with the bit pattern 1001 in bits 7 through 4.

MUL Rd, Rm, Rs

MLA Rd, Rm, Rs, Rn

The decoder detects these forms before treating the same general bit region as an ordinary data-processing instruction.

LDM and STM Instructions

Load Multiple and Store Multiple use a 16-bit register-list field. Each bit corresponds to one ARM register.

Register list bit 0  → r0
Register list bit 1  → r1
...
Register list bit 15 → pc

This makes instructions such as stack saves and restores compact.

ARM SVC Instruction

SVC, historically called SWI in older ARM terminology, uses a 24-bit immediate field and requests a supervisor/service operation whose exact meaning depends on the execution environment.

0xEF000000

Decoded:
SVC #0

A32 vs Thumb vs AArch64

These instruction sets must not be decoded with one shared 32-bit template. A32 is the classic 32-bit ARM instruction set. Thumb/T32 uses different 16-bit and 32-bit encodings. AArch64/A64 is a separate instruction set used by 64-bit ARM execution state.

If a supplied word matches an instruction family outside this decoder's supported A32 subset, the tool reports it as unknown or extension-specific rather than generating misleading assembly.

ARM Instruction Decoder FAQs

How many bits is an ARM A32 instruction?

An A32 instruction is 32 bits or four bytes.

Does this tool decode Thumb instructions?

No. Thumb and Thumb-2 use different encodings and are outside this A32 decoder.

Does this tool decode AArch64 instructions?

No. AArch64/A64 uses a different instruction set and encoding structure.

What do bits 31–28 mean in ARM A32?

For many classic A32 instructions they contain the four-bit condition code.

What does condition E mean?

Condition hexadecimal E is binary 1110, traditionally AL or always.

What register is r13?

r13 is conventionally the stack pointer, SP.

What register is r14?

r14 is the link register, LR.

What register is r15?

r15 represents the program counter, PC, in classic A32 register naming.

What is the difference between B and BL?

B performs a branch. BL performs Branch with Link and records a return address in the link register.

Why can't the decoder show an absolute branch address?

An absolute target requires the address where the instruction itself is located. With only the instruction word, the decoder can reliably show the encoded PC-relative displacement.

What does BX LR usually do?

BX LR branches to the address held in the link register and is commonly used as a return sequence in suitable ARM code.

How are ARM immediate constants encoded?

Many A32 data-processing immediate operands use an eight-bit value rotated right by an even number of bit positions.

What is the S bit?

For applicable data-processing instructions, the S bit controls whether condition flags are updated.

What does L mean in LDR/STR encoding?

L equal to 1 selects a load and L equal to 0 selects a store.

Can I enter little-endian ARM bytes?

Yes. Select Little-Endian Bytes and enter four bytes such as 01 00 80 E0.

Decode 32-Bit ARM A32 Machine Instructions

Enter one ARM instruction word to inspect its assembly operation, condition code, registers, immediate data, memory addressing controls, branch displacement and exact 32-bit representation.