CAN Bit Timing Calculator

What Is a CAN Bit Timing Calculator?

A CAN Bit Timing Calculator determines the timing parameters required by a Controller Area Network controller to achieve a desired nominal bus bitrate. A CAN controller does not normally receive a setting such as “500 kbit/s” alone. Its hardware uses a clock divider and a number of time segments to construct each transmitted and received bit.

The important parameters commonly include the Bit Rate Prescaler (BRP), Time Segment 1 (TSEG1), Time Segment 2 (TSEG2), Synchronization Jump Width (SJW), the number of time quanta per bit, and the resulting sample point.

This calculator searches combinations that fit the selected controller timing limits and ranks them according to bitrate accuracy and closeness to the desired sample point.

How to Use the CAN Bit Timing Calculator

CAN Bit Timing Formula

A CAN bit is divided into time quanta. In the simplified functional timing model used by this calculator:

The additional one time quantum represents the synchronization segment at the start of every bit.

What Is a CAN Time Quantum?

The time quantum, usually abbreviated TQ or tq, is the basic timing unit from which a CAN controller constructs one bit period.

The CAN clock is divided by the bit-rate prescaler. The resulting time quantum is then repeated for the synchronization segment, TSEG1, and TSEG2.

CAN Sample Point Formula

CAN receivers sample the bus near the boundary between TSEG1 and TSEG2. Using functional timing values, the sample point is:

The synchronization segment is included before TSEG1, so the numerator contains one additional time quantum.

500 kbit/s CAN Timing Example

Suppose the controller timing clock is 16 MHz and the target nominal bitrate is 500 kbit/s with an 87.5% sample point.

What Are TSEG1 and TSEG2?

Bosch M_CAN documentation explicitly defines nominal TSEG1 as the combination of Prop_Seg and Phase_Seg1, while TSEG2 represents Phase_Seg2.

What Is CAN SJW?

SJW means Synchronization Jump Width. It limits how much a CAN controller may lengthen or shorten a bit segment during resynchronization.

The usable SJW range is controller-specific, and SJW must be compatible with the phase timing. This calculator prevents the suggested SJW from exceeding TSEG2 or the selected controller-profile limit.

What Does BRP Mean in CAN?

BRP stands for Bit Rate Prescaler. It divides the CAN controller timing clock to create the duration of one time quantum.

An important implementation detail is that CAN controller registers often use encoded values. For example, a register field of zero may represent a functional prescaler of one, while a programmed register value of one may represent a functional prescaler of two.

Bosch M_CAN Bit Timing

Bosch M_CAN provides a wide nominal timing range. In functional terms, its nominal prescaler can range from 1 to 512 clock periods, while the programmable timing segments provide substantially larger ranges than many older Classical CAN controllers.

The M_CAN documentation states that the nominal bit time is formed from the synchronization segment plus the programmable segments before and after the sample point.

CAN Controller Limits Matter

There is no single universal set of BRP and timing-segment limits for every CAN controller. Older controllers may allow relatively small TSEG1, TSEG2 and SJW ranges, while newer CAN/CAN FD IP blocks may support much larger values.

The generic profile is a search convenience rather than a promise that every controller supports every displayed value. Always verify hardware limits.

What Is CAN Bitrate Error?

A requested bitrate may not always be exactly obtainable from a particular CAN clock and the available integer timing values.

An exact zero-error configuration is preferable whenever the controller clock allows one. If an exact configuration is unavailable, acceptable tolerance depends on the complete CAN network timing budget.

Why the Sample Point Matters

The sample point determines how far into a CAN bit the receiver waits before deciding whether the bus is recessive or dominant. Moving it later provides more time before sampling for propagation through the bus, transceivers and nodes.

However, a later sample point leaves a smaller TSEG2 interval after sampling. The best setting therefore depends on bitrate, oscillator tolerance, physical network length, transceiver delays and controller restrictions.

Typical CAN Bitrates

CAN Clock Frequency vs CPU Clock

Do not automatically enter the microcontroller’s CPU frequency. The CAN peripheral may receive its clock through a peripheral clock tree, PLL, divider, oscillator source or dedicated CAN clock.

For example, a processor running at 160 MHz could still supply an 80 MHz, 40 MHz or another frequency to its CAN peripheral. The timing calculation must use the frequency seen by the CAN bit timing logic.

Why Two CAN Nodes Can Use Different Timing Values

Two CAN nodes do not necessarily need identical BRP and time-segment register values. Different microcontrollers can have different clock frequencies and different CAN controller implementations.

What matters is that the resulting nominal bit rate and network timing are compatible. A 16 MHz controller and an 80 MHz controller can communicate at 500 kbit/s using different internal timing configurations.

CAN Bit Timing vs CAN FD Data Timing

CAN FD can use separate timing for the nominal arbitration phase and the faster data phase. Modern CAN FD controllers therefore commonly expose a nominal bit timing configuration and a separate data bit timing configuration.

This page is focused on the nominal CAN bit timing problem: finding BRP, TSEG1, TSEG2, SJW and sample point for a requested CAN bitrate. It does not duplicate a separate CAN FD data-phase timing calculator.

Common CAN Bit Timing Mistakes

CAN Bit Timing Calculator FAQs