MIPS 32-Bit Machine Code Utility

MIPS Instruction Decoder

Decode a 32-bit MIPS instruction from hexadecimal, binary, decimal or little-endian byte input. Inspect opcode, instruction format, source and destination registers, shift amount, funct code, immediate values, branch displacement and jump target fields.

✓ R-Type ✓ I-Type ✓ J-Type ✓ Branch Offsets ✓ Register Aliases

MIPS

Decode 32-Bit MIPS Instruction

● Ready

32-Bit MIPS Instruction Enter one 32-bit instruction word. Example: 0x012A4020.

Input Format Little-endian mode accepts four bytes such as 20 40 2A 01.

Decoder scope: this page decodes common classic 32-bit MIPS/MIPS32 instruction formats. Some coprocessor, privileged, DSP, MIPS64 and architecture-extension instructions use additional encoding tables and are reported conservatively when they are outside this tool’s implemented subset.

MIPS Instruction Decode Result Decoded

Decoded Instruction —

Instruction Hex —

Unsigned Decimal —

Instruction Type —

Opcode —

rs —

rt —

rd —

shamt —

funct —

Immediate —

Target / Offset —

Little-Endian Bytes —

32-Bit Instruction Binary

—

Field	Bits	Binary	Decimal	Meaning

Bit-Level Decode Breakdown

—

What Is a MIPS Instruction Decoder?

A MIPS Instruction Decoder converts a 32-bit machine-code word into its assembly-level fields. Depending on the opcode, the instruction can use R-type, I-type or J-type encoding.

The decoder extracts the six-bit opcode first and then interprets the remaining bits according to the selected instruction family.

MIPS 32-Bit Instruction Width

Classic MIPS instructions use fixed-width 32-bit instruction words.

32 bits
= 4 bytes
= 8 hexadecimal digits

The fixed width makes it possible to identify major fields directly by their bit positions.

MIPS R-Type Instruction Format

31      26 25    21 20    16 15    11 10    6 5       0
+----------+--------+--------+--------+-------+---------+
|  opcode  |   rs   |   rt   |   rd   | shamt | funct  |
+----------+--------+--------+--------+-------+---------+
   6 bits     5        5        5        5       6

For many R-type arithmetic instructions the major opcode is zero, while the lowest six-bit funct field identifies the operation.

Example: ADD $t0, $t1, $t2

Machine code:
0x012A4020

Opcode:
000000 → SPECIAL / R-Type

rs:
01001 → register 9 → $t1

rt:
01010 → register 10 → $t2

rd:
01000 → register 8 → $t0

shamt:
00000

funct:
100000 → 0x20 → ADD

Common MIPS R-Type Function Codes

Funct	Instruction
0x00	SLL
0x02	SRL
0x03	SRA
0x08	JR
0x09	JALR
0x0C	SYSCALL
0x20	ADD
0x21	ADDU
0x22	SUB
0x23	SUBU
0x24	AND
0x25	OR
0x26	XOR
0x27	NOR
0x2A	SLT
0x2B	SLTU

MIPS I-Type Instruction Format

31      26 25    21 20    16 15                    0
+----------+--------+--------+-----------------------+
|  opcode  |   rs   |   rt   |      immediate       |
+----------+--------+--------+-----------------------+
   6 bits     5        5              16 bits

I-type format is used by immediate arithmetic, logical instructions, branches, loads and stores.

Signed vs Unsigned Immediate Interpretation

The meaning of the 16-bit immediate depends on the instruction.

ADDI / ADDIU:
signed 16-bit immediate

LW / SW:
signed 16-bit address offset

BEQ / BNE:
signed branch displacement

ANDI / ORI / XORI:
zero-extended 16-bit immediate

LUI:
immediate placed in upper 16 bits

MIPS Load and Store Addressing

Load and store instructions combine a base register with a signed 16-bit offset.

lw $t0, 4($sp)

Base:
$sp

Offset:
4

Effective address:
contents($sp) + 4

MIPS Branch Offset Calculation

Conditional branch instructions such as BEQ and BNE contain a signed 16-bit offset measured in words relative to the instruction after the branch.

byte displacement =
SignExtend(immediate) << 2

target =
PC + 4 + byte displacement

Because the calculator does not know the actual address of the instruction, it reports the displacement relative to PC + 4.

MIPS J-Type Instruction Format

31      26 25                                      0
+----------+-----------------------------------------+
|  opcode  |             target[25:0]                |
+----------+-----------------------------------------+
   6 bits                  26 bits

J and JAL use pseudo-direct addressing. The 26-bit field is shifted left by two positions and combined with upper address bits derived from PC + 4.

MIPS Jump Target Formula

jump_low_28 =
target_field << 2

full target =
(PC + 4)[31:28] |
jump_low_28

Without the instruction's PC address, the decoder can reliably report the encoded low 28-bit target component but cannot invent the upper four bits.

MIPS Register Numbers and Names

Number	Name	Common Role
0	$zero	Constant zero
1	$at	Assembler temporary
2–3	$v0–$v1	Return values
4–7	$a0–$a3	Arguments
8–15	$t0–$t7	Temporaries
16–23	$s0–$s7	Saved registers
24–25	$t8–$t9	Temporaries
28	$gp	Global pointer
29	$sp	Stack pointer
30	$fp / $s8	Frame pointer / saved register
31	$ra	Return address

Example: JR $ra

Instruction:
0x03E00008

Opcode:
0

rs:
31 → $ra

funct:
0x08 → JR

Decoded:
JR $ra

This is a commonly seen function-return pattern in classic MIPS code.

MIPS Little-Endian Instruction Bytes

A 32-bit instruction is often shown as one hexadecimal word, but on a little-endian MIPS system its bytes appear in reverse significance order in memory.

Instruction:
0x012A4020

Little-endian bytes:
20 40 2A 01

Select Little-Endian Bytes when analyzing a raw memory dump containing bytes in that order.

Example: ADDI

Instruction:
0x2128000A

Opcode:
001000 → ADDI

rs:
$t1

rt:
$t0

Immediate:
10

Decoded:
ADDI $t0, $t1, 10

Example: LUI

LUI loads the 16-bit immediate into the upper half of the target register.

LUI $t0, 0x1234

Resulting value contribution:
0x12340000

The lower sixteen bits are cleared by the LUI operation.

MIPS Instruction Decoder Scope

The opcode space contains instructions from multiple MIPS revisions and extensions. This tool prioritizes common classic integer instructions used in education, disassembly, embedded firmware and basic machine-code analysis.

If an opcode or function code is outside the implemented subset, the tool still shows the raw fields but marks the instruction as unknown or extension-specific rather than assigning an unsupported mnemonic.

MIPS Instruction Decoder FAQs

How many bits is a MIPS instruction?

Classic MIPS instructions are 32 bits wide.

How many bits is the MIPS opcode?

The major opcode occupies bits 31 through 26 and is six bits wide.

What are the three basic MIPS instruction formats?

They are R-type, I-type and J-type.

What does opcode 0 mean in MIPS?

Opcode zero usually selects the SPECIAL R-type encoding space, where the lowest six-bit funct field identifies the operation.

What is the funct code for ADD?

Classic R-type ADD uses funct value 0x20.

What is the funct code for SUB?

Classic R-type SUB uses funct value 0x22.

What is register 29 in MIPS?

What is register 31?

How is a MIPS branch target calculated?

The signed 16-bit immediate is shifted left by two and added to PC + 4.

Why can't the decoder give a full J instruction address?

J and JAL reuse the upper four bits of PC + 4, so the instruction's runtime address is required to reconstruct the complete 32-bit target.

Does ANDI sign-extend its immediate?

No. ANDI, ORI and XORI use a zero-extended 16-bit immediate.

Does LW use a signed offset?

Yes. The 16-bit load/store address offset is sign-extended.

Can I enter little-endian MIPS bytes?

Yes. Select Little-Endian Bytes and enter exactly four bytes such as 20 40 2A 01.

Does this decoder support every MIPS extension?

No. It focuses on common classic MIPS32 integer instructions and reports unimplemented extension patterns conservatively.

Decode MIPS Machine Instructions

Enter one 32-bit MIPS instruction to inspect its assembly operation, opcode, register fields, function code, shift amount, immediate value, branch displacement, jump target bits and little-endian byte representation.