I2S Digital Audio Clock Utility

I2S Audio Clock Calculator

Calculate I2S bit clock, LRCLK/sample clock and master clock frequencies from audio sample rate, channel count, sample width, slot width and MCLK ratio. Also inspect frame size, clock periods, payload data rate and slot efficiency.

✓ BCLK ✓ LRCLK ✓ MCLK ✓ Frame Bits ✓ Audio Data Rate ✓ Clock Periods

I2S

Audio Clock Calculation

● Ready

Sample Rate (Hz) LRCLK normally equals the audio sample rate.

Channels / Slots Per Frame Standard stereo I2S normally uses two slots per audio frame.

Audio Sample Width (bits) Number of meaningful audio bits in each sample.

I2S Slot Width (bits) BCLK is based on transmitted slot width, not only meaningful sample bits.

MCLK Ratio Master-clock ratio required by the codec, DAC, ADC or audio PLL.

Custom MCLK Ratio (optional) If entered, this value overrides the MCLK Ratio dropdown.

Clock formula: BCLK = sample rate × slots per frame × slot width. For ordinary stereo I2S with two 32-bit slots at 48 kHz, BCLK is 48,000 × 2 × 32 = 3.072 MHz. MCLK is calculated independently from the selected MCLK = Fs × ratio.

I2S Audio Clock Result Calculated

Required I2S Bit Clock —

LRCLK / Fs —

BCLK —

MCLK —

MCLK Ratio —

Bits Per Frame —

Meaningful Audio Bits / Frame —

Audio Payload Rate —

Wire Bit Rate —

Slot Efficiency —

LRCLK Period —

BCLK Period —

MCLK Period —

BCLK / LRCLK —

MCLK / BCLK —

Unused Bits / Slot —

Clock Configuration —

Calculation Breakdown

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What Is an I2S Audio Clock?

I2S is a synchronous serial interface commonly used to transport digital audio between processors, codecs, ADCs, DACs and other audio devices. The interface normally uses a serial data signal together with a bit clock and a word or left/right clock.

Many audio systems also provide a higher-frequency master clock used internally by an audio converter or codec.

I2S LRCLK or Word Select Clock

LRCLK, often called WS or word select, identifies the audio frame and left/right channel timing. For conventional stereo I2S, one complete left-plus-right frame occurs per audio sample period.

Sample Rate:
48,000 samples/s

LRCLK:
48,000 Hz
= 48 kHz

I2S BCLK Formula

The serial bit clock must clock every transmitted bit slot in each audio frame. Therefore BCLK depends on the slot width rather than only the number of useful sample bits.

BCLK =
Fs × Number of Slots × Slot Width

48 kHz Stereo 32-Bit Slot Example

Sample Rate:
48,000 Hz

Channels / Slots:
2

Slot Width:
32 bits

Frame:
2 × 32
= 64 bits

BCLK:
48,000 × 64
= 3,072,000 Hz

BCLK:
3.072 MHz

Sample Width vs Slot Width

Sample width describes how many audio bits contain meaningful sample data. Slot width describes how many serial bit clocks are allocated to each channel within the frame.

Audio sample:
24 bits

I2S slot:
32 bits

Unused / padding:
8 bits per slot

A 24-bit audio stream carried inside 32-bit slots therefore uses the same BCLK as 32-bit audio when the frame structure remains two 32-bit slots.

I2S MCLK Formula

Master clock is commonly specified as a multiple of the audio sample rate. The exact required ratio depends on the codec, converter or audio clocking architecture.

MCLK =
Fs × MCLK Ratio

Common MCLK Ratios

Ratio	44.1 kHz MCLK	48 kHz MCLK
128 × Fs	5.6448 MHz	6.144 MHz
256 × Fs	11.2896 MHz	12.288 MHz
384 × Fs	16.9344 MHz	18.432 MHz
512 × Fs	22.5792 MHz	24.576 MHz

44.1 kHz Audio Clock Example

For two 32-bit slots and an MCLK ratio of 256:

Fs:
44,100 Hz

BCLK:
44,100 × 2 × 32
= 2,822,400 Hz
= 2.8224 MHz

MCLK:
44,100 × 256
= 11,289,600 Hz
= 11.2896 MHz

48 kHz Audio Clock Example

Fs:
48,000 Hz

32-bit stereo slots:
64 bits/frame

BCLK:
3.072 MHz

MCLK at 256 Fs:
12.288 MHz

96 kHz I2S Example

Fs:
96,000 Hz

2 × 32-bit slots:
64 bits/frame

BCLK:
96,000 × 64
= 6.144 MHz

MCLK at 256 Fs:
24.576 MHz

192 kHz I2S Example

Fs:
192,000 Hz

2 × 32-bit slots:
64 bits/frame

BCLK:
192,000 × 64
= 12.288 MHz

MCLK at 256 Fs:
49.152 MHz

Audio Payload Data Rate

The meaningful audio payload rate excludes unused slot padding and is calculated from the actual sample width.

Audio Payload Rate =
Fs × Channels × Sample Bits

For 48 kHz stereo 24-bit audio:

48,000 × 2 × 24
= 2,304,000 bits/s
= 2.304 Mbit/s

I2S Wire Bit Rate

The serialized wire rate is equivalent to BCLK when one data bit is transferred per bit-clock cycle.

Wire Bit Rate =
Fs × Slots × Slot Width

For 48 kHz stereo with 32-bit slots:

3.072 Mbit/s

Slot Efficiency

When sample width is smaller than slot width, part of each audio slot consists of unused or padding bits.

Efficiency =
Sample Bits / Slot Bits × 100%

24-bit audio in 32-bit slots:

24 / 32 × 100
= 75%

I2S Clock Period

The calculator also converts each clock frequency into its period using:

Period =
1 / Frequency

For a 3.072 MHz BCLK, one clock cycle is approximately 325.52 nanoseconds.

BCLK to LRCLK Ratio

The BCLK-to-LRCLK ratio directly equals the number of transmitted bit clocks in one audio frame.

BCLK / LRCLK =
Channels × Slot Width

Stereo × 32-bit slots:

2 × 32
= 64

Therefore:
BCLK = 64 × LRCLK

MCLK to BCLK Ratio

A useful hardware check is the ratio between the master clock and bit clock. For example, a 256 Fs MCLK combined with a 64 Fs BCLK gives:

MCLK / BCLK =
256 / 64
= 4

Whether a particular clock relationship is supported depends on the audio device and its clock-divider or PLL configuration.

I2S vs Left-Justified Audio

I2S and left-justified interfaces can use the same sample rate, slot width and clock frequencies while differing in the alignment of audio data relative to the word-select transition.

This calculator handles clock-rate mathematics. It does not assume that a particular BCLK frequency proves the interface is using I2S rather than another serial audio alignment mode.

I2S and TDM Slots

Standard I2S is normally associated with stereo left and right slots, but many audio peripherals extend similar serial-clock concepts to TDM interfaces with four, eight or more slots.

48 kHz
8 slots
32 bits each

BCLK =
48,000 × 8 × 32

= 12.288 MHz

The channel/slot input is therefore configurable, but verify the actual framing mode supported by your hardware.

I2S Audio Clock Calculator FAQs

How do I calculate I2S BCLK?

Multiply sample rate by the number of slots in each frame and by the number of bits in each slot.

Is LRCLK equal to the sample rate?

For conventional I2S audio framing, LRCLK or word-select frequency corresponds to the audio sample rate.

What is BCLK for 48 kHz stereo with 32-bit slots?

48,000 × 2 × 32 gives 3.072 MHz.

What is MCLK for 48 kHz at 256 Fs?

48,000 × 256 gives 12.288 MHz.

What is MCLK for 44.1 kHz at 256 Fs?

44,100 × 256 gives 11.2896 MHz.

Should I use sample width or slot width for BCLK?

Use the transmitted slot width. A 24-bit sample carried in a 32-bit slot still uses 32 bit-clock periods for that slot.

Does 24-bit stereo always require 48 BCLK cycles per frame?

No. It depends on slot width. Two tightly packed 24-bit slots require 48 clocks, while two 32-bit slots require 64.

Is MCLK required by I2S itself?

The serial I2S transfer uses BCLK and word select, while MCLK is commonly required by codecs or converters for their internal clocking. Requirements depend on the device.

What does 64 Fs BCLK mean?

It means there are 64 bit-clock cycles for every audio sample frame. Stereo audio with two 32-bit slots is a common example.

Can this calculator be used for TDM audio?

The clock formula also works for a specified number of TDM-style slots, but the exact data framing and synchronization rules must be checked against the hardware protocol.

Calculate I2S BCLK, LRCLK and MCLK

Determine digital-audio clock frequencies, frame width, data rate, clock periods and slot efficiency for common I2S and related synchronous audio interfaces.