MMU Address Translation Utility

Virtual Address & Page Table Calculator

Decode a virtual address into page offset, virtual page number and multi-level page-table indices. Use architecture presets for x86-64, 32-bit x86, RISC-V Sv39 and Sv48, or define a custom paging layout. Optional PFN and page-table base inputs can also calculate physical and PTE addresses.

✓ VPN + Offset ✓ Page Indices ✓ x86-64 ✓ Sv39 / Sv48 ✓ PTE Address ✓ Physical Address

Virtual Address Decode

● Ready

Virtual Address Hexadecimal, binary and unsigned decimal input are accepted.

Paging Layout Preset determines address bits, page offset and page-table index widths.

Virtual Address Bits Number of address bits decoded by this layout.

Page Offset Bits 12 offset bits correspond to a 4 KiB page.

Page-Table Level Bits Enter index widths from highest level to lowest, for example 9,9,9,9.

Physical Page Frame Number — Optional If supplied, Physical Address = PFN × Page Size + Page Offset.

Page Table Entry Size Used with the optional page-table base address.

Selected Page-Table Base — Optional Base of one specific page-table page whose entry address you want to calculate.

Index Used for PTE Address PTE Address = Table Base + Selected Index × PTE Size.

Paging model: the page offset contains the low address bits and is not translated by the page table. The remaining virtual page number bits are split into page-table indices. Architecture-specific permissions, huge pages, canonical-address rules, TLB behavior and actual page-table contents are outside the basic bit-field calculation unless explicitly represented by the selected preset.

Virtual Address & Page Table Result Calculated

Virtual Page Number / Offset —

Virtual Address —

Page Size —

Page Offset —

Virtual Page Number —

Address Bits —

Offset Bits —

Page Table Levels —

Page Alignment —

Physical Address —

PFN —

Selected PTE Address —

Layout —

Virtual Address Bit Layout

Field	Bit Range	Width	Binary	Hex	Decimal

Address Calculation Breakdown

—

What Is a Virtual Address & Page Table Calculator?

A Virtual Address & Page Table Calculator separates a virtual memory address into the fields used by a paged memory-management system. The low bits form the offset within a page, while the upper address bits identify a virtual page and, in multi-level systems, individual page-table indices.

This is useful when studying operating systems, MMUs, virtual memory, kernel debugging, x86 paging, RISC-V address translation, page-table walks and low-level memory-management code.

Virtual Address Translation Basics

With fixed-size pages, a virtual address can be separated conceptually into two parts:

Virtual Address
= Virtual Page Number + Page Offset

The page offset identifies a byte inside a page. The virtual page number is translated through one or more page tables to obtain a physical page frame.

Page Offset Formula

When the page size is a power of two, the number of page-offset bits is the base-2 logarithm of the page size.

Page Size = 4096 bytes

4096 = 2^12

Page Offset Bits = 12

For a 4 KiB page, therefore, virtual-address bits 11 through 0 form the page offset.

Virtual Page Number Formula

VPN = Virtual Address >> OffsetBits

For 4 KiB pages:

VPN = Virtual Address >> 12

The page offset can also be calculated with a mask:

Offset
= Virtual Address & (PageSize - 1)

Example: 32-Bit Address with 4 KiB Pages

Virtual Address:
0x12345ABC

Page Size:
0x1000

Offset:
0xABC

Virtual Page Number:
0x12345

Page-Aligned Virtual Address:
0x12345000

Why Multi-Level Page Tables Are Used

A single flat page table for a large virtual address space can require an extremely large number of entries even when most virtual pages are unused. Multi-level paging divides the virtual page number into multiple indexes.

Virtual Address:

[ Level 4 ]
[ Level 3 ]
[ Level 2 ]
[ Level 1 ]
[ Offset  ]

Each level selects an entry from a table that leads toward the next level or eventually toward a translated physical page.

x86-64 4-Level Virtual Address Layout

With standard 4 KiB pages and the traditional 48-bit x86-64 virtual-address layout, the low 48 bits are divided into four nine-bit table indexes and a 12-bit page offset.

47        39 38        30 29        21 20        12 11         0
+-----------+------------+------------+------------+-------------+
|   PML4    |    PDPT    |     PD     |     PT     |   Offset    |
+-----------+------------+------------+------------+-------------+
    9 bits      9 bits       9 bits       9 bits       12 bits

x86-64 Page Table Index Formulas

PML4 Index = (VA >> 39) & 0x1FF
PDPT Index = (VA >> 30) & 0x1FF
PD Index   = (VA >> 21) & 0x1FF
PT Index   = (VA >> 12) & 0x1FF
Offset     = VA & 0xFFF

Each nine-bit index can represent values from 0 through 511.

32-Bit x86 Two-Level Paging

A classic 32-bit x86 page table with 4 KiB pages divides the 32-bit virtual address into a 10-bit page-directory index, a 10-bit page-table index and a 12-bit offset.

31                    22 21                    12 11             0
+-----------------------+------------------------+----------------+
| Page Directory Index  |   Page Table Index     | Page Offset    |
+-----------------------+------------------------+----------------+
        10 bits                  10 bits               12 bits

RISC-V Sv39 Address Breakdown

Sv39 uses three nine-bit virtual page number components together with a 12-bit page offset.

38        30 29        21 20        12 11         0
+-----------+------------+------------+-------------+
|   VPN[2]  |   VPN[1]   |   VPN[0]   |   Offset    |
+-----------+------------+------------+-------------+
    9 bits      9 bits       9 bits       12 bits

The calculator labels these as three page-table levels and extracts each index separately.

RISC-V Sv48 Address Breakdown

Sv48 extends the virtual page number with a fourth nine-bit component.

47        39 38        30 29        21 20        12 11        0
+-----------+------------+------------+------------+------------+
|   VPN[3]  |   VPN[2]   |   VPN[1]   |   VPN[0]   |  Offset   |
+-----------+------------+------------+------------+------------+
    9 bits      9 bits       9 bits       9 bits      12 bits

Physical Address from a Page Frame Number

Once translation produces a physical page frame number, the physical address is formed by combining that page frame with the unchanged page offset.

Physical Address
= PFN × Page Size + Page Offset

Equivalent:

Physical Address
= (PFN << OffsetBits) | Offset

Example Physical Address Calculation

PFN:
0x12345

Page Size:
0x1000

Page Offset:
0xABC

Physical Page Base:
0x12345000

Physical Address:
0x12345ABC

Page Table Entry Address Calculation

When the physical or virtual base address of a specific page-table page is already known, the address of one entry in that table can be calculated from the table index and entry size.

PTE Address
= Page Table Base
+ (Index × PTE Size)

For a table with 8-byte entries and index 100:

Entry Offset:
100 × 8
= 800 bytes
= 0x320

PTE Address:
Table Base + 0x320

Page-Aligned Address

A page-aligned virtual address has all page-offset bits cleared.

Page Base
= VA & ~(PageSize - 1)

For a 4 KiB page:

0x12345ABC
→ page base 0x12345000

Page Size and Offset Bits

Page Size	Offset Bits
1 KiB	10
4 KiB	12
16 KiB	14
64 KiB	16
2 MiB	21
1 GiB	30

The actual supported page sizes and corresponding page-table interpretation depend on the processor architecture and translation mode.

Huge Pages and Large Pages

A multi-level page-table walk does not always continue to the lowest level. Architectures may permit an upper-level entry to map a larger page directly. When that happens, some address bits that normally serve as lower-level indexes instead become part of the offset within the large page.

This calculator’s standard presets show the normal 4 KiB-page field layout. Huge-page translation requires selecting or defining the corresponding larger page offset.

Canonical Virtual Addresses

Architectures can impose validity requirements beyond simple field extraction. For example, an architecture may use fewer virtual-address bits than the machine register width and require unused high bits to follow a particular canonical form.

The calculator focuses primarily on the translation fields contained within the configured virtual-address width. A numerically decomposable address does not automatically prove that software is allowed to access it.

Virtual Address vs Physical Address

A virtual address is generated by software or the processor’s execution environment. A physical address identifies a location in the physical address space after translation.

Virtual Address
       ↓
Virtual Page Number
       ↓
Page Table Translation
       ↓
Physical Page Frame Number
       ↓
+ Original Page Offset
       ↓
Physical Address

What Is a TLB?

A Translation Lookaside Buffer caches recent address translations so the processor does not need to perform a complete page-table walk for every memory access.

The TLB changes translation performance, but it does not change the underlying virtual-address bit fields shown by this calculator.

Why This Calculator Uses BigInt

JavaScript Number values can represent only integers up to 53 bits of precision exactly. Virtual and physical addresses can be wider than that. This calculator therefore uses integer arithmetic that preserves hexadecimal addresses beyond the normal JavaScript safe-integer range.

Example:

0xFFFF800012345678

must not be silently rounded before
page-table fields are extracted.

Virtual Address & Page Table Calculator FAQs

What is a virtual page number?

The virtual page number is the part of a virtual address above the page-offset bits. It identifies the virtual page being translated.

How do I calculate the page offset?

For a power-of-two page size, mask the low log2(page size) bits of the virtual address.

How many offset bits does a 4 KiB page use?

A 4 KiB page is 4096 bytes or 2^12 bytes, so it uses 12 page-offset bits.

How do I calculate the VPN?

Shift the virtual address right by the number of page-offset bits.

How many indices are in standard x86-64 four-level paging?

The normal 4 KiB-page layout has four nine-bit indexes: PML4, PDPT, PD and PT.

How many entries can a 9-bit page-table index select?

Nine bits can encode 512 values, so the index can select entries 0 through 511.

What is the classic 32-bit x86 layout?

With 4 KiB pages it uses a 10-bit page-directory index, a 10-bit page-table index and a 12-bit offset.

What is the RISC-V Sv39 layout?

Sv39 uses three nine-bit VPN indexes and a 12-bit offset for the normal 4 KiB page layout.

What is the RISC-V Sv48 layout?

Sv48 uses four nine-bit VPN indexes plus a 12-bit page offset.

How is a physical address calculated from a PFN?

Shift the physical frame number left by the page-offset width and combine it with the original page offset.

How is a PTE address calculated?

If the table base is already known, multiply the selected table index by the page-table-entry size and add that byte offset to the table base.

Does this calculator read actual page tables from memory?

No. It performs address and field calculations only. It does not access the processor’s MMU or operating-system page-table contents.

Does it support huge pages?

Custom layouts can model different offset widths, but the standard presets represent their ordinary 4 KiB-page field breakdown.

Why are the page-offset bits unchanged by translation?

Virtual and physical pages are aligned to the same selected page size, so the byte position inside the page is carried directly into the physical address.

Can this tool handle 64-bit-style addresses?

Yes. Address arithmetic and bit extraction use BigInt rather than imprecise floating-point integer arithmetic.

Decode Virtual Memory Addresses

Break virtual addresses into page-table indexes, VPN and page offsets, then optionally calculate physical addresses and selected page-table-entry addresses for common and custom paging layouts.