IRQ Embedded Timing Utility

Interrupt Latency Calculator

Calculate interrupt latency from CPU frequency and execution-cycle delays. Estimate hardware exception-entry time, interrupt-disabled blocking, higher-priority ISR delay, software dispatch overhead, total response time and practical interrupt-rate limits.

✓ CPU Cycles ✓ IRQ Entry ✓ Critical Section ✓ Higher-Priority ISR ✓ Response Time ✓ Max IRQ Rate

IRQ

Interrupt Response Timing

● Ready

CPU / Core Frequency (Hz) Clock frequency used to convert execution cycles into elapsed time.

Hardware Interrupt Entry Cycles Cycles from interrupt acceptance to normal ISR execution under the modeled conditions.

Current Instruction Completion Cycles Worst-case remaining cycles before the processor can accept the interrupt.

Interrupt-Disabled / Critical Section Cycles Optional blocking time while the target interrupt cannot be serviced.

Higher-Priority ISR Blocking Cycles Worst-case cycles consumed by higher-priority interrupt work before this ISR runs.

Software Dispatch / Wrapper Cycles Optional RTOS, vector-wrapper, trampoline or software dispatcher overhead.

ISR Prologue Cycles Compiler-generated register save or manual ISR setup before useful work begins.

ISR Useful Work Cycles Estimated cycles spent performing the actual interrupt service.

ISR Epilogue / Exit Cycles Cycles required to restore context and return from the ISR.

CPU Budget Allowed for This ISR (%) Used to estimate a safer interrupt frequency based on ISR execution cost.

Latency model:

Total latency cycles = current-instruction delay + critical-section blocking + higher-priority ISR blocking + hardware entry + software dispatch + ISR prologue

. This models time until the ISR reaches its useful work. CPU architecture, memory wait states, cache behavior, bus contention and interrupt-controller details can add further variation.

Interrupt Latency Result Calculated

Worst-Case Modeled Time to Useful ISR Work —

CPU Cycle Time —

Total Latency Cycles —

Total Interrupt Latency —

Hardware Entry Time —

Instruction Delay —

Critical-Section Delay —

Higher-Priority ISR Delay —

Software + Prologue —

ISR Execution Cycles —

ISR Execution Time —

Full IRQ Occupancy —

Theoretical Max ISR Rate —

Budgeted ISR Rate —

CPU Time at 1 kHz —

Latency Frequency Equivalent —

CPU Budget —

Latency Calculation Breakdown

—

What Is Interrupt Latency?

Interrupt latency is the delay between an interrupt event becoming eligible for service and the processor reaching the code that responds to that event. It is an important timing parameter in real-time and embedded systems.

Latency can include processor exception-entry overhead, completion of the current instruction, temporarily disabled interrupts, higher-priority interrupts and software dispatch overhead.

Interrupt Latency Formula

Total Latency Cycles =

Current Instruction Delay
+ Critical-Section Blocking
+ Higher-Priority ISR Blocking
+ Hardware Interrupt Entry
+ Software Dispatch
+ ISR Prologue

The corresponding time is found by dividing the total number of cycles by the CPU clock frequency.

Convert CPU Cycles to Time

Cycle Time = 1 / CPU Frequency

Time =
Cycles / CPU Frequency

For a 120 MHz processor, one ideal CPU cycle is approximately 8.333 nanoseconds.

120 MHz Example

CPU:
120 MHz

Current instruction:
3 cycles

Hardware interrupt entry:
12 cycles

Software dispatch:
8 cycles

ISR prologue:
10 cycles

No additional blocking

Latency cycles:
3 + 12 + 8 + 10
= 33 cycles

Latency:
33 / 120,000,000

= 275 ns

Current Instruction Completion

An interrupt may arrive while the processor is already executing another instruction. Depending on the architecture and instruction, the processor may have to complete or reach an interruptible boundary before exception handling starts.

For deterministic analysis, use the worst-case relevant instruction delay rather than only the average instruction duration.

Critical Sections and Disabled Interrupts

Software can temporarily mask interrupts while manipulating shared data or performing timing-sensitive operations. An interrupt arriving during such a section cannot be serviced until the blocking interval ends.

Critical section:
500 cycles

CPU:
100 MHz

Blocking time:

500 / 100,000,000

= 5 µs

A long critical section can therefore dominate interrupt latency even when the processor’s native hardware interrupt-entry time is very short.

Higher-Priority Interrupt Blocking

In a prioritized interrupt system, a higher-priority ISR can run before the target interrupt. The target ISR’s response can therefore be delayed by the execution of higher-priority interrupt work.

Worst-case real-time analysis can require accounting for more than one higher-priority interrupt arrival, depending on the scheduling and interrupt model.

Hardware Interrupt Entry Cycles

Hardware interrupt entry commonly includes interrupt recognition, state saving, vector lookup and pipeline changes. The exact cycle count is processor-specific.

Do not assume that one architectural headline latency number applies under all conditions. Flash wait states, memory placement, stacking behavior and bus activity can alter actual measurements.

ISR Prologue Overhead

After the CPU reaches the interrupt vector, compiler-generated code may save additional registers or create a stack frame before the first useful application instruction executes.

Hardware entry:
12 cycles

Compiler prologue:
10 cycles

Actual application work begins after:
22 cycles

before considering other blocking.

Software Interrupt Dispatch

Some systems enter a generic interrupt handler before branching to a device-specific function. RTOS interrupt wrappers, vector trampolines and software dispatch tables can therefore add extra latency.

Enter those cycles in the Software Dispatch field when modeling such a system.

ISR Execution Time

Interrupt latency and ISR execution time are related but different. Latency describes how long the system waits before useful interrupt servicing starts, while execution time describes how long the ISR itself occupies the processor.

ISR execution cycles =

Prologue
+ Useful ISR Work
+ Epilogue

Full Interrupt Occupancy

For a simplified single-interrupt event, full processor occupancy can include the latency path plus the useful ISR work and return overhead.

Full IRQ Occupancy =

Instruction Delay
+ Blocking
+ Hardware Entry
+ Software Dispatch
+ Prologue
+ Useful Work
+ Epilogue

This is useful when estimating how frequently an ISR could run before consuming excessive CPU time.

Maximum Interrupt Rate

A purely theoretical rate can be estimated by assuming the processor does nothing except execute the modeled ISR path:

Theoretical Maximum Rate =

1
-------------------
Full ISR Occupancy

Real applications should operate well below this limit because foreground software, other interrupts, RTOS activity and timing margin also consume CPU.

Interrupt CPU Budget

The calculator also estimates an interrupt frequency corresponding to the selected percentage of CPU time.

Budgeted IRQ Rate =

CPU Budget Fraction
-------------------
ISR Execution Time

For example, allowing an ISR to consume no more than 20% of CPU time produces a much lower frequency limit than assuming 100% CPU occupancy.

Interrupt CPU Load Formula

CPU Load =

ISR Rate × ISR Time × 100%

If a complete ISR execution occupies 5 µs and runs 1,000 times per second, the ISR consumes approximately 0.5% of one CPU.

Interrupt Latency vs Response Time

Interrupt latency normally ends when the ISR begins servicing the event. Application response time can be longer if useful work occurs later inside the ISR or is deferred to a task, thread, DMA completion or scheduler.

When the requirement specifies time until an actual device action occurs, include all processing between the interrupt event and that action.

Interrupt Jitter

Interrupt latency can vary from event to event. That variation is commonly described as latency jitter. Sources include different instruction boundaries, nested interrupts, cache state, memory wait states, DMA or bus contention and critical-section timing.

This calculator produces a deterministic value from the delays you enter. For worst-case analysis, enter worst-case rather than average cycle counts.

Interrupt Latency Measurement

A common practical measurement technique is to trigger an external event, toggle a GPIO near the start of the ISR and measure the delay with an oscilloscope or logic analyzer.

Measurement captures hardware and software effects that can be difficult to derive from nominal instruction-cycle counts alone.

DMA vs Interrupt Processing

DMA can reduce the number of interrupts required for high-rate data transfer by moving blocks of data without processor intervention for every individual item.

The CPU can then service completion or threshold events instead of responding to every byte, sample or peripheral transaction.

Interrupt Latency Calculator FAQs

How do I calculate interrupt latency from CPU cycles?

Add the relevant blocking, entry, dispatch and prologue cycles, then divide the total by the processor clock frequency.

What is the cycle time of a 100 MHz CPU?

An ideal 100 MHz clock has a period of 10 nanoseconds per cycle.

What is the cycle time of a 120 MHz CPU?

One ideal 120 MHz CPU cycle is approximately 8.333 nanoseconds.

Does interrupt latency include ISR execution time?

Usually latency refers to the delay before interrupt servicing begins. ISR execution time is a separate quantity, although both contribute to total response and CPU occupancy.

Do disabled interrupts increase latency?

Yes. If the target interrupt is masked, it must wait until interrupts are enabled again.

Can another ISR increase latency?

Yes. Higher-priority interrupt handlers can delay lower-priority interrupt service.

Why can measured interrupt latency vary?

Instruction boundaries, nesting, memory wait states, cache state, bus contention and software masking can cause event-to-event variation.

How can I measure interrupt latency?

One approach is to generate a known external event, toggle a GPIO at ISR entry and measure the time difference with an oscilloscope or logic analyzer.

What is interrupt jitter?

Interrupt jitter is the variation in latency or response time across repeated interrupt events.

Can this calculator model an RTOS interrupt wrapper?

Yes. Add the RTOS or software-dispatch overhead in the Software Dispatch / Wrapper Cycles field.

Calculate MCU Interrupt Latency and ISR Response

Convert processor cycles into interrupt delay, ISR execution time, total CPU occupancy and practical interrupt-rate estimates for embedded and real-time systems.