128 BIT SD Register Utility

SD Card CSD Register Decoder

Decode a 128-bit Secure Digital Card-Specific Data register from hexadecimal bytes. Inspect CSD structure, card capacity, block size, transfer rate, command classes, erase characteristics and write-protection flags for SDSC, SDHC and SDXC cards.

✓ CSD v1.0 ✓ CSD v2.0 ✓ Capacity ✓ Block Length ✓ Transfer Speed ✓ Erase Fields
CSD
SD Card-Specific Data Register
● Ready
Enter exactly 16 bytes / 128 bits. Spaces, commas, colons, hyphens and continuous hexadecimal are accepted. Enter bytes from CSD bits 127:120 first through bits 7:0 last.
Use reverse mode only when your tool or firmware dumps the CSD bytes in reverse order.
CSD structure: bits 127:126 select the CSD format. Structure 0 uses the older SDSC capacity formula based on C_SIZE, C_SIZE_MULT and READ_BL_LEN. Structure 1 uses the SDHC/SDXC capacity formula (C_SIZE + 1) × 512 KiB.
SD CSD Decode Result Decoded
Decoded Card-Specific Data
CSD Structure
Card Family
Capacity
Capacity Bytes
C_SIZE
Read Block Length
Transfer Speed
TAAC
NSAC
Command Classes
Erase Block Enabled
Sector Size
Write Block Length
Permanent WP
Temporary WP
CRC7
Raw Register
Field Breakdown

What Is the SD Card CSD Register?

CSD stands for Card-Specific Data. It is a 128-bit SD card register containing information needed by a host to understand storage capacity, transfer characteristics, supported command classes, erase behavior, block lengths and certain protection capabilities.

The exact interpretation of several fields depends on the CSD structure version.

SD Card CSD Register Size

CSD length: 128 bits = 16 bytes = 32 hexadecimal digits

The register is conventionally numbered from bit 127 down to bit 0.

CSD_STRUCTURE Field

Bits 127:126 identify the CSD structure.

Bits 127:126 Structure Typical Card
00CSD Version 1.0SDSC
01CSD Version 2.0SDHC / SDXC
10 / 11Reserved or newer contextSpecification dependent

SDHC and SDXC Capacity Formula

For CSD Version 2.0, the capacity calculation is much simpler than the older SDSC format.

Memory Capacity = (C_SIZE + 1) × 512 KiB

The C_SIZE field occupies bits 69:48 in the Version 2.0 CSD layout.

SDHC Capacity Example

Suppose C_SIZE is 30,719:

Capacity = (30,719 + 1) × 512 KiB = 30,720 × 524,288 bytes = 16,106,127,360 bytes ≈ 15 GiB ≈ 16.1 GB

Commercial card labels normally use decimal gigabytes, while operating systems may display binary GiB or use a mixture of conventions.

SDSC Capacity Formula

CSD Version 1.0 cards calculate capacity using C_SIZE, C_SIZE_MULT and READ_BL_LEN.

READ_BL_LEN: Read block length = 2^READ_BL_LEN bytes MULT: 2^(C_SIZE_MULT + 2) BLOCKNR: (C_SIZE + 1) × MULT Capacity: BLOCKNR × Read Block Length

READ_BL_LEN

READ_BL_LEN defines the maximum read data block length as a power of two.

READ_BL_LEN = 9 Block length: 2^9 = 512 bytes

For high-capacity cards, host addressing semantics are standardized differently from the original byte-addressed SDSC model, even though the CSD still exposes defined block-related fields.

WRITE_BL_LEN

WRITE_BL_LEN describes the maximum write data block length in the same power-of-two style.

Write Block Length = 2^WRITE_BL_LEN bytes

TRAN_SPEED

The TRAN_SPEED field describes the card’s maximum data transfer rate using a coded time/value multiplier and unit.

The decoder interprets the standard coded transfer-rate table and shows the nominal rate represented by the field.

TAAC

TAAC is the Data Read Access Time 1 field. It uses a coded time-value and time unit. It is primarily relevant to the timing model used by earlier card generations.

For newer high-capacity operation, some legacy timing fields are fixed or less important to normal high-speed host operation.

NSAC

NSAC represents Data Read Access Time 2 in units of 100 clock cycles.

NSAC delay = NSAC field × 100 clock cycles

CCC — Card Command Classes

The twelve-bit CCC field indicates which command classes are supported by the card.

CCC: Bits 95:84 Each set bit indicates support for a command class.

The decoder displays the raw 12-bit value so it can be compared with the command classes required by a host implementation.

ERASE_BLK_EN

ERASE_BLK_EN indicates whether erase operations can use single-block units or whether larger erase-sector rules apply.

ERASE_BLK_EN = 1 Single block can be used as erase unit under the applicable SD erase rules.

SECTOR_SIZE

The SECTOR_SIZE field participates in defining erase-sector characteristics. Its exact practical significance depends on the CSD structure and the erase behavior specified for the card generation.

The decoder reports both the encoded field and its conventional block-count interpretation.

Permanent Write Protection

The PERM_WRITE_PROTECT bit indicates whether permanent card-level write protection has been enabled.

This is different from the mechanical lock switch found on full-size SD card adapters, which is interpreted by the host rather than being a security state stored in the flash medium itself.

Temporary Write Protection

TMP_WRITE_PROTECT is a temporary write-protection flag in the CSD. It should not be confused with file-system permissions or the mechanical write-protect tab.

SD Card CRC7

The low portion of the CSD contains a seven-bit CRC field followed by the end bit. The CRC is used as part of SD command/register integrity mechanisms.

Bits 7:1: CRC7 Bit 0: End bit

SDHC vs SDSC CSD

Feature SDSC / CSD v1 SDHC / SDXC / CSD v2
Capacity calculation C_SIZE + multiplier + block length (C_SIZE + 1) × 512 KiB
C_SIZE width 12 bits 22 bits
Addressing model Historically byte-addressed Block-addressed
Typical capacity Standard capacity High / extended capacity

Why SD Card Advertised Capacity Looks Different

Card manufacturers commonly advertise capacity using decimal units where 1 GB equals 1,000,000,000 bytes. Binary units use powers of 1024, where 1 GiB equals 1,073,741,824 bytes.

32,000,000,000 bytes Decimal: 32 GB Binary: ≈ 29.8 GiB

File-system formatting and reserved card-management areas can further affect the usable capacity shown to the operating system.

CSD vs CID Register

The CSD describes card operating and storage characteristics. The CID register contains card identification information such as manufacturer and product identity fields.

They are separate 128-bit SD registers and should not be decoded with the same field map.

CSD vs OCR Register

The OCR register describes operating-voltage and card-power-up information, including capacity-status related signaling during initialization. It does not contain the same detailed storage geometry fields as the CSD.

SD Card CSD Register Decoder FAQs

How many bits are in the SD CSD register?
The SD Card-Specific Data register contains 128 bits, or 16 bytes.
How do I know whether a CSD is Version 1 or Version 2?
Check bits 127:126. Binary 00 identifies CSD Version 1.0 and 01 identifies Version 2.0.
How is SDHC capacity calculated?
For CSD Version 2.0, capacity is calculated as (C_SIZE + 1) × 512 KiB.
How is SDSC capacity calculated?
Version 1.0 combines C_SIZE, C_SIZE_MULT and READ_BL_LEN to determine the number of blocks and bytes.
What does READ_BL_LEN 9 mean?
It corresponds to a block length of 2^9 bytes, or 512 bytes.
What does TRAN_SPEED mean?
It is a coded field representing the nominal maximum transfer rate supported by the card under the corresponding SD timing model.
What is CCC?
CCC is the 12-bit Card Command Classes field showing which SD command classes are supported.
Does CSD write protection equal the mechanical lock switch?
No. Permanent and temporary write-protect bits are CSD fields. The physical lock tab on an SD adapter is detected by the host separately.
Can the CSD tell me the exact usable file-system capacity?
It describes card storage capacity, but file-system formatting, reserved regions and manufacturer conventions can make the usable volume appear smaller.
Can I decode CID data with this tool?
No. CID uses a different 128-bit register format and should be decoded with a dedicated CID decoder.

Decode SD Card Capacity and CSD Fields

Inspect raw SD CSD values from microcontroller firmware, Linux utilities, embedded drivers and card diagnostics with automatic handling of SDSC and SDHC/SDXC capacity formulas.

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