PCIe Transaction Layer Utility

PCIe TLP Decoder

Decode PCI Express Transaction Layer Packet headers from hexadecimal bytes. Inspect TLP format, type, traffic class, attributes, length, Requester ID, Tag, byte enables, memory address, configuration target, completion status and packet payload.

✓ Memory TLP ✓ I/O TLP ✓ Config TLP ✓ Completion ✓ 3DW / 4DW ✓ Payload

TLP

PCI Express Header Decoder

● Ready

PCIe TLP Hex Bytes Enter TLP bytes in packet order. Spaces, commas, colons and hyphens are accepted. Continuous hexadecimal and 0x-prefixed bytes are also supported. Do not include DLLP, framing symbols or physical-layer encoding.

Input Interpretation Use DWORD little-endian mode only when each captured 32-bit word is byte-reversed.

Payload Display

Decoder scope: this page parses the conventional PCIe TLP header beginning with the Fmt/Type byte. It does not expect data-link framing, LCRC, sequence number, STP/END symbols or PHY encoding. Newer optional prefixes and generation-specific extensions can require additional protocol context.

PCIe TLP Decode Result Decoded

Transaction Layer Packet —

TLP Type —

Header Format —

Fmt —

Type Code —

Length —

Traffic Class —

Attributes —

TH / TD / EP —

Address Type —

Requester ID —

Tag —

Byte Enables —

Address —

Completer ID —

Completion Status —

Payload —

Header DWORDs —

Payload Data —

Field Breakdown —

What Is a PCIe TLP?

A PCI Express Transaction Layer Packet, or TLP, carries transactions between PCIe devices. Memory reads, memory writes, configuration accesses, completions, I/O operations and messages are represented using TLPs.

A TLP begins with a transaction-layer header. Most common requests use a 3-DWORD or 4-DWORD header, optionally followed by data.

PCIe TLP Header Size

3DW header:
3 × 32 bits
= 96 bits
= 12 bytes

4DW header:
4 × 32 bits
= 128 bits
= 16 bytes

A 64-bit Memory Request normally uses a four-DWORD header because two DWORDs are required for the address.

Fmt and Type Fields

The first TLP byte contains the Format and Type information. The three-bit Fmt field indicates header length and whether a data payload is present. The five-bit Type field identifies the transaction class.

Byte 0:

Bits 7:5 = Fmt
Bits 4:0 = Type

Common Fmt Values

Fmt	Header	Data
000	3DW	No Data
001	4DW	No Data
010	3DW	Data Present
011	4DW	Data Present

Memory Read TLP

A Memory Read request contains a Requester ID, Tag, byte enables and target memory address. Because a Memory Read does not carry the requested data itself, it normally uses a no-data Fmt value.

Memory Read 32:

DW0:
Fmt / Type / Length

DW1:
Requester ID
Tag
Last DW BE
First DW BE

DW2:
32-bit Address

Memory Write TLP

A Memory Write uses a request header similar to Memory Read but includes the write data immediately after the header.

Memory Write:

Header
+
Payload DWORDs

The Length field describes the data payload in DWORD units.

32-Bit vs 64-Bit Memory Address

Memory requests can contain either a 32-bit or 64-bit address. The Fmt field determines whether the request header uses three or four DWORDs.

3DW Memory Request:
DW2 = Address[31:2] + low reserved bits

4DW Memory Request:
DW2 = Address[63:32]
DW3 = Address[31:2] + low reserved bits

The decoder reports the aligned address represented by the header.

PCIe TLP Length

The Length field occupies ten bits in the first DWORD and represents the transaction length in DWORDs for the common packet formats handled here.

1 DWORD = 4 bytes

Length = 4

Payload size:
4 × 4
= 16 bytes

For standard TLP interpretation, an encoded Length value of zero represents 1024 DWORDs rather than zero DWORDs.

Requester ID

Requester ID identifies the PCIe function that generated a request. It contains Bus, Device and Function fields.

Requester ID:

Bits 15:8 = Bus
Bits 7:3  = Device
Bits 2:0  = Function

For example, Requester ID 0x1234 corresponds to bus, device and function fields derived from that 16-bit value.

PCIe Tag

The Tag helps associate a non-posted request with its completion. Multiple outstanding reads can therefore be distinguished even when they originate from the same Requester ID.

Tag interpretation can be extended by PCIe features beyond the conventional 8-bit field, so full interpretation can depend on device capabilities.

First and Last DWORD Byte Enables

The First DW BE and Last DW BE fields indicate which bytes within the first and last requested DWORDs are active.

Byte Enable:
1111 = all four bytes enabled

0001 = byte 0 enabled

0011 = bytes 0 and 1 enabled

For a one-DWORD request, Last DW BE normally has no active-byte meaning and the First DW BE controls the valid bytes.

Traffic Class

The three-bit Traffic Class field can be used with PCIe Quality of Service mechanisms to differentiate transaction traffic.

TC range:
0 through 7

TLP Attributes

TLP attributes include transaction properties such as Relaxed Ordering and No Snoop. Their interpretation is spread across header bits in conventional TLP headers.

The decoder displays the combined attribute value and its basic flag interpretation.

TD and ECRC

The TD bit indicates the presence of a TLP Digest. When present, an additional DWORD containing the End-to-End CRC follows the packet data.

This page identifies the TD flag but does not automatically validate ECRC.

EP — Poisoned TLP

The EP bit indicates that the TLP is marked as poisoned. Poisoning allows an error associated with transaction data to propagate through the PCIe system.

A poisoned packet should be interpreted together with PCIe error reporting and the surrounding transaction context.

PCIe Configuration TLP

Configuration requests access PCI or PCI Express configuration space. Type 0 requests target devices on the local bus while Type 1 configuration requests are used for routing through bridges.

Configuration Request Header:

Requester ID
Tag
Byte Enables
Bus Number
Device Number
Function Number
Register Number

Configuration Type 0 vs Type 1

TLP	Typical Purpose
CfgRd0 / CfgWr0	Configuration access to device on destination bus
CfgRd1 / CfgWr1	Configuration access routed toward another bus

PCIe Completion TLP

A Completion is generated in response to a non-posted request such as a Memory Read or Configuration Read. The header can identify the Completer, completion status, byte count, Requester ID, Tag and lower address.

Completion With Data

Completion with Data, often shown as CplD, contains returned payload bytes after the three-DWORD completion header.

CplD:

Completion Header
+
Returned Data

PCIe Completion Status

Status Code	Meaning
000	Successful Completion
001	Unsupported Request
010	Configuration Request Retry Status
100	Completer Abort

Other encodings are reserved or revision-dependent and should not be assigned a different meaning without protocol context.

Completer ID

Completion packets contain a Completer ID identifying the function that generated the completion. Like Requester ID, it can be separated into Bus, Device and Function numbers.

PCIe TLP Payload

When Fmt indicates that data is present, bytes following the decoded TLP header are treated as payload by this tool. The payload can be displayed as raw hexadecimal bytes or grouped into 32-bit DWORDs.

The decoder also compares the available payload bytes with the Length field and warns in the detailed breakdown when the packet appears truncated.

PCIe TLP vs DLLP

TLPs belong to the Transaction Layer and carry actual PCIe transactions. Data Link Layer Packets, or DLLPs, perform link-management functions such as flow control and acknowledgement.

A DLLP should not be pasted into this TLP decoder as though its first byte were a TLP Fmt/Type byte.

TLP Header vs LCRC

A captured PCIe packet can include data-link information beyond the transaction-layer contents. In decoded protocol-analyzer output, the TLP header is typically separated from sequence numbers and LCRC.

Only the actual TLP bytes should be supplied to this tool.

PCIe TLP Decoder FAQs

What is a PCIe TLP?

A PCI Express Transaction Layer Packet carries transactions such as memory accesses, configuration accesses, messages and completions between PCIe functions.

What is a 3DW TLP header?

It is a transaction header containing three 32-bit DWORDs, for a total of 12 bytes.

What is a 4DW TLP header?

It contains four DWORDs, or 16 bytes, and is commonly used when a memory request requires a 64-bit address.

What does the PCIe Fmt field mean?

Fmt identifies the basic TLP header length and whether the packet carries a data payload.

What does the Type field mean?

Type identifies the transaction class, such as Memory, I/O, Configuration or Completion.

What does the TLP Length field represent?

For the common TLPs decoded here, it represents the transaction length in DWORDs. An encoded value of zero represents 1024 DWORDs.

What is Requester ID?

Requester ID identifies the PCIe function originating the request and contains Bus, Device and Function information.

What is a PCIe TLP Tag?

The Tag allows a requester to distinguish outstanding non-posted transactions and match returned completions.

What does EP mean in a TLP?

EP means Error/Poisoned. A set EP bit indicates that the TLP has been marked poisoned.

Can this decoder replace a PCIe protocol analyzer?

No. It interprets common raw TLP header fields. Complete PCIe analysis also requires link context, capabilities, sequence handling, flow control, transaction matching, prefixes and generation-specific protocol rules.

Decode PCI Express TLP Headers

Inspect raw PCIe transaction-layer bytes from FPGA simulations, endpoint logs, root-complex traces and protocol analyzers with field-level decoding for common request and completion packets.