BAR PCI Express Resource Utility

PCIe BAR Size Calculator

Decode PCI Express Base Address Registers and calculate the address-space size reported by a BAR probe mask. Analyze Memory BARs, I/O BARs, 32-bit and 64-bit BARs, prefetchable capability, alignment and configured address ranges.

✓ BAR Mask ✓ 32-Bit BAR ✓ 64-Bit BAR ✓ I/O BAR ✓ Prefetchable ✓ Address Range

BAR

PCIe Resource Decoder

● Ready

BAR Low DWORD After Size Probe Enter the value read back after writing all 1s to the BAR with decoding disabled.

BAR High DWORD for 64-Bit BAR Used only when the low BAR reports a 64-bit Memory BAR.

Input Format

Configured BAR Low DWORD Current BAR register value assigned by firmware or the operating system.

Configured BAR High DWORD Used for a 64-bit Memory BAR.

Known BAR Size Enter the known resource size to calculate the mapped end address.

Size Unit

BAR sizing method: software disables the relevant decoder, writes all 1s to the BAR, reads back the implemented address bits, masks off BAR attribute bits and computes size = (~mask + 1) within the BAR’s address width. The original BAR value must be restored afterward.

PCIe BAR Result Calculated

Decoded BAR —

BAR Type —

Memory Type —

Prefetchable —

Low DWORD —

High DWORD —

Address Mask —

BAR Size —

Size Bytes —

Alignment —

Base Address —

End Address —

Address Width —

Raw Attribute Bits —

Power-of-Two Size —

Required BAR Registers —

Range —

Calculation Breakdown —

What Is a PCIe BAR?

A Base Address Register, or BAR, is a PCI or PCI Express configuration-space register used to describe a device resource that must be mapped into system Memory or I/O address space.

PCIe endpoints commonly use Memory BARs for register windows, device memory, framebuffers, DMA control structures and other memory-mapped resources.

How PCIe BAR Sizing Works

BAR size is traditionally discovered by saving the BAR value, disabling the corresponding resource decoder, writing all ones, reading the value back and examining which address bits are hardwired to zero.

1. Save BAR value
2. Disable Memory or I/O decoding
3. Write 0xFFFFFFFF
4. Read BAR back
5. Mask attribute bits
6. Compute size
7. Restore original BAR

A 64-bit Memory BAR requires the corresponding upper BAR DWORD to be included in the sizing operation.

PCIe BAR Size Formula

After removing the non-address attribute bits, the basic sizing calculation is:

Size = (~BAR_Mask + 1)

within the implemented BAR address width

The same relationship can also be written as two’s-complement negation of the masked probe value.

4 KiB BAR Example

Probe readback:
0xFFFFF004

Memory BAR attribute bits:
0x4

Address mask:
0xFFFFF000

Invert + 1:

~0xFFFFF000 + 1
= 0x00001000

BAR size:
4096 bytes
= 4 KiB

PCIe Memory BAR Bit Layout

Memory BAR low DWORD:

Bit 0:
0 = Memory BAR

Bits 2:1:
Memory type

Bit 3:
Prefetchable

Bits 31:4:
Base address bits

Memory BAR Type Bits

Bits 2:1	Meaning
00	32-bit Memory BAR
01	Legacy below-1-MB encoding
10	64-bit Memory BAR
11	Reserved

32-Bit Memory BAR

A conventional 32-bit Memory BAR occupies one BAR register and exposes address bits in bits 31 through 4. The resulting resource must be aligned to its implemented size.

Configured BAR:
0x80000000

Base address:
0x80000000

64-Bit PCIe BAR

A 64-bit Memory BAR consumes two consecutive BAR registers. The low BAR holds the type and prefetchable flags plus the low address bits, while the next BAR holds address bits 63 through 32.

BAR n:
Low 32 bits + attributes

BAR n+1:
Upper 32 address bits

The combined base address can therefore extend above the 4 GiB boundary.

PCIe I/O BAR

If bit 0 is one, the BAR represents I/O space rather than Memory space. For an I/O BAR, the low address bits have a different reserved/attribute layout.

I/O BAR:

Bit 0:
1 = I/O space

Bits 1:
Reserved / implementation-defined legacy field

Address mask:
typically bits 31:2

Prefetchable BAR

Bit 3 of a Memory BAR indicates whether reads can be prefetched without causing device side effects. Prefetchable resources are commonly used for device memory where speculative reads are safe.

Control/status register regions with read side effects are normally non-prefetchable.

BAR Alignment Requirement

A BAR’s assigned base address must normally be naturally aligned to the size of the resource.

BAR size:
64 KiB

Required base alignment:
64 KiB

Valid:
0x80000000
0x80010000

Not naturally aligned:
0x80008000

64 KiB BAR Size Example

Address mask:
0xFFFF0000

Size:

~0xFFFF0000 + 1
= 0x00010000

= 65,536 bytes
= 64 KiB

1 MiB BAR Size Example

Address mask:
0xFFF00000

Size:

~0xFFF00000 + 1
= 0x00100000

= 1,048,576 bytes
= 1 MiB

Configured BAR Address

When a BAR contains its assigned address rather than a size-probe result, attribute bits must be masked before interpreting the base address.

Memory BAR:
0x80000004

Low attribute bits:
0x4

Base address:
0x80000000

Calculate BAR Address Range

When the base and size are known, the inclusive mapped address range is:

End Address =

Base Address
+ BAR Size
- 1

For a 4 KiB BAR mapped at 0x80000000:

Start:
0x80000000

End:
0x80000FFF

Why BAR Sizes Are Powers of Two

The BAR mask mechanism naturally represents resource sizes as powers of two with corresponding natural alignment. Implemented address bits form a mask whose trailing zero region determines the allocation size.

PCIe device designs should follow the applicable BAR sizing requirements for the resource type being implemented.

BAR Registers in PCIe Configuration Space

Type 0 configuration headers used by endpoints provide a set of BAR register locations beginning at configuration offset 0x10. A 64-bit BAR consumes two adjacent 32-bit entries, reducing the number of independent BAR resources that can be represented.

BAR0, BAR1, BAR2 and Other BAR Numbers

Names such as BAR0 and BAR2 refer to the position of a Base Address Register within the PCI configuration header. They do not by themselves determine the BAR’s size or type.

For example, BAR0 can be 32-bit or 64-bit depending on the type bits returned by the device.

Why a 64-Bit BAR Uses Two Registers

A configuration BAR register is only 32 bits wide. A 64-bit resource therefore requires both the current BAR register and the immediately following BAR register to hold the complete address.

Software must treat the pair as one logical BAR.

PCIe BAR Size Calculator FAQs

How do I calculate PCIe BAR size?

Write all ones during a proper BAR sizing probe, read back the implemented address mask, remove attribute bits, then calculate its two’s-complement size.

What does BAR bit 0 mean?

Bit 0 distinguishes Memory space from I/O space. Zero indicates a Memory BAR, while one indicates an I/O BAR.

How do I know if a BAR is 64-bit?

For a Memory BAR, bits 2:1 equal binary 10 when the BAR uses a 64-bit address.

Does a 64-bit BAR use two BAR registers?

Yes. The low BAR contains attributes and lower address bits, while the next BAR contains the upper 32 address bits.

What does prefetchable mean?

It indicates that speculative or prefetched reads are safe for that memory resource according to PCI/PCIe resource semantics.

Why must a BAR address be aligned to its size?

The BAR mask represents a naturally aligned power-of-two resource window, so the assigned base must respect the corresponding alignment.

What does a mask of 0xFFFFF000 mean?

For a 32-bit Memory BAR address mask, it corresponds to a 4 KiB resource.

What does 0xFFFF0000 correspond to?

A 32-bit Memory BAR mask of 0xFFFF0000 corresponds to 64 KiB.

Can I calculate the end address from a BAR?

Yes, if the configured base and resource size are known. The inclusive end address is base + size − 1.

Should software leave all ones written to a BAR?

No. A proper sizing procedure saves the original BAR, performs the probe under the required decode conditions, and restores the original value afterward.

Calculate PCIe BAR Size and Address Range

Decode PCI Express BAR probe results and configured resource addresses for endpoint development, FPGA validation, driver debugging and PCIe configuration analysis.