CSR RISC-V Register Utility

RISC-V CSR Decoder

Decode RISC-V Control and Status Register addresses and values. Inspect common Machine and Supervisor CSRs including mstatus, misa, mtvec, mie, mip, mcause, mepc, sstatus, stvec, scause, sepc and satp with RV32 and RV64 support.

✓ mstatus ✓ misa ✓ mtvec ✓ mcause ✓ mie / mip ✓ satp

CSR

Control & Status Register Decoder

● Ready

CSR Address or Name Enter a 12-bit CSR address or a supported CSR name.

CSR Value Hexadecimal, binary and decimal values are accepted.

RISC-V XLEN XLEN affects fields such as MXL, interrupt bit position, SATP and status fields.

Value Input Format

CSR address format: RISC-V CSR instructions carry a 12-bit CSR address. Bits 11:10 describe the basic read/write class and bits 9:8 encode the lowest privilege level that can access the CSR. Individual register values then use CSR-specific field layouts.

RISC-V CSR Decode Result Decoded

Decoded Register —

CSR Name —

CSR Address —

XLEN —

Privilege —

Access Class —

Primary Field 1 —

Primary Field 2 —

Primary Field 3 —

Primary Field 4 —

Primary Field 5 —

Primary Field 6 —

Binary Value —

Decimal Value —

CSR Class Bits —

Known Register —

Decoded Fields —

Calculation Breakdown —

What Is a RISC-V CSR?

CSR means Control and Status Register. RISC-V defines a dedicated CSR address space used for processor status, trap handling, interrupt control, counters, virtual-memory configuration, identification and implementation-specific control.

CSR instructions such as CSRRW, CSRRS and CSRRC access registers using a 12-bit CSR address embedded in the instruction.

RISC-V CSR Address Size

CSR address width:
12 bits

Range:
0x000 through 0xFFF

Maximum CSR addresses:
4096

CSR Privilege Encoding

Bits 9 and 8 of the CSR address indicate the lowest privilege level allowed to access the register.

Address Bits 9:8	Privilege
00	User
01	Supervisor
10	Reserved / Hypervisor-related context
11	Machine

CSR Read-Only Address Encoding

CSR address bits 11:10 classify the conventional CSR access range. Values with bits 11:10 equal to binary 11 belong to the read-only CSR address class. Other address classes are conventionally read/write.

CSR[11:10] = 11
→ read-only address class

CSR[11:10] = 00, 01 or 10
→ read/write address class

mstatus CSR

The machine status register contains global machine-state controls used for interrupt handling and privilege transitions.

Important fields include MIE, MPIE, MPP, SIE, SPIE, SPP, MPRV, SUM, MXR and extension-state fields such as FS and XS.

mstatus Interrupt Bits

MIE:
Machine Interrupt Enable
bit 3

MPIE:
Previous MIE
bit 7

MPP:
Previous privilege mode
bits 12:11

Trap entry and return instructions modify these fields as part of privilege state transitions.

misa CSR

The Machine ISA register can describe the base RISC-V register width and implemented standard ISA extensions.

misa:

MXL:
Most-significant field

Extension bits:
A = bit 0
B = bit 1
C = bit 2
...
I = bit 8
M = bit 12
...

A set extension bit corresponds to the alphabetic extension identified by that bit position.

misa MXL Field

For common implementations, the MXL field indicates the native register width.

MXL	Meaning
1	RV32
2	RV64
3	RV128 encoding

mtvec CSR

The machine trap-vector register contains a trap-handler base address and MODE field.

mtvec:

BASE =
value with low two bits removed

MODE =
bits 1:0

MODE 0 is Direct. MODE 1 is Vectored. Other mode values depend on the supported architecture specification and implementation.

mie and mip CSRs

The Machine Interrupt Enable register controls individual interrupt classes, while Machine Interrupt Pending reflects pending interrupt conditions.

Common bits:

SSIP / SSIE = bit 1
MSIP / MSIE = bit 3

STIP / STIE = bit 5
MTIP / MTIE = bit 7

SEIP / SEIE = bit 9
MEIP / MEIE = bit 11

mcause CSR

mcause records the reason for a trap taken into Machine mode. Its highest bit distinguishes interrupts from synchronous exceptions, while the remaining bits contain the cause code.

Interrupt =
mcause[XLEN-1]

Cause Code =
mcause[XLEN-2:0]

Common RISC-V Exception Cause Codes

Code	Exception
0	Instruction address misaligned
1	Instruction access fault
2	Illegal instruction
3	Breakpoint
4	Load address misaligned
5	Load access fault
6	Store/AMO address misaligned
7	Store/AMO access fault
8	Environment call from U-mode
9	Environment call from S-mode
11	Environment call from M-mode
12	Instruction page fault
13	Load page fault
15	Store/AMO page fault

Common Interrupt Cause Codes

Code	Interrupt
1	Supervisor software interrupt
3	Machine software interrupt
5	Supervisor timer interrupt
7	Machine timer interrupt
9	Supervisor external interrupt
11	Machine external interrupt

mepc and sepc

The machine and supervisor exception program-counter registers contain the address associated with trap handling and return.

Their effective alignment depends on the implemented instruction alignment and ISA extensions.

mtval and stval

Trap-value registers provide additional information about certain exceptions. Depending on the cause, the value can hold a faulting address, instruction information or zero.

satp CSR

The Supervisor Address Translation and Protection register controls supervisor-level virtual-memory translation where supported.

Its layout differs between RV32 and RV64.

RV64 satp Layout

RV64 satp:

MODE:
bits 63:60

ASID:
bits 59:44

PPN:
bits 43:0

MODE selects the address-translation scheme. For example, common standardized values include Bare and paged translation modes such as Sv39, Sv48 and Sv57.

RV32 satp Layout

RV32 satp:

MODE:
bit 31

ASID:
bits 30:22

PPN:
bits 21:0

sstatus CSR

sstatus is the supervisor-visible status register. It exposes the Supervisor-level status fields relevant to S-mode rather than every machine status bit.

Commonly examined fields include SIE, SPIE, SPP, FS, XS, SUM and MXR.

medeleg and mideleg

Machine exception delegation and interrupt delegation registers allow supported traps to be delegated from Machine mode to Supervisor mode.

Each implemented bit corresponds to a cause number that can potentially be delegated according to the architecture’s rules.

RISC-V CSR Decoder FAQs

How wide is a RISC-V CSR address?

The CSR address encoded by CSR instructions is 12 bits wide, giving addresses from 0x000 through 0xFFF.

What is CSR 0x300?

0x300 is the standard machine status register, mstatus.

What is CSR 0x301?

0x301 is misa, the Machine ISA register.

What is CSR 0x305?

0x305 is mtvec, the Machine Trap-Vector Base-Address register.

What is CSR 0x342?

0x342 is mcause, which records the cause of a trap taken into Machine mode.

How do I know whether mcause is an interrupt?

The most significant bit of mcause is the interrupt flag. The remaining bits contain the cause code.

What does misa contain?

misa can report the machine register width and alphabetically encoded standard ISA extension bits.

What does mtvec MODE 1 mean?

The standard MODE value 1 selects vectored trap handling.

What is satp used for?

satp controls Supervisor address translation and protection, including the virtual-memory mode, ASID and root page-table physical page number.

Can every CSR value be decoded identically on every RISC-V processor?

No. Some fields are optional, WARL, reserved, extension-dependent or implementation-specific. The tool performs detailed decoding for common standard CSRs and preserves unknown registers as raw values.

Decode RISC-V Control and Status Registers

Inspect raw CSR values from RISC-V firmware, debuggers, OpenOCD, emulators, FPGA cores, kernel logs and exception traces with automatic decoding of common machine and supervisor registers.