SR FF Sequential Logic Simulator

SR Flip-Flop Simulator

Simulate a clocked SR flip-flop online. Set the S and R inputs, initialize the stored Q state and trigger clock pulses to test hold, set, reset and invalid conditions while tracking Q and Q̅.

✓ Set / Reset ✓ Clock Pulse ✓ Q / Q̅ ✓ Hold State ✓ Invalid Detection ✓ State History

Clocked SR Flip-Flop

● Ready

Input Controls

Set Input S

Reset Input R

Stored State & Clock

Current Q 0

Current Q̅ 1

Initialize Stored State

CLK = 0 · waiting

Simulation model: This page uses an active-high, rising-edge SR flip-flop. The S and R values are sampled when the clock pulse is triggered. S=0,R=0 holds the previous Q; 1,0 sets Q; 0,1 resets Q; and 1,1 is treated as the forbidden/invalid SR condition.

S = 1 and R = 1 is the forbidden state for this active-high SR flip-flop model. Q and Q̅ are not assigned a valid complementary next state.

SR Flip-Flop Result Hold

Next State —

Set S —

Reset R —

Previous Q —

Next Q —

Next Q̅ —

Operation —

Clock Edge —

State Valid —

S = 0

R = 0

CLK ↑

SR
FLIP-FLOP Rising Edge

Q = 0

Q̅ = 1

Pulse	S	R	Previous Q	Next Q	Q̅	Operation

State Transition Analysis —

Characteristic Logic —

SR Flip-Flop Simulator

The SR Flip-Flop Simulator demonstrates the behavior of a Set-Reset sequential logic element. Unlike a combinational gate whose output depends only on current inputs, a flip-flop stores state, so its next output can depend on both its inputs and its previous Q value.

This simulator uses an active-high SR model sampled on a rising clock edge. You can select S and R, initialize Q to either zero or one and trigger successive clock pulses to watch the stored state change.

The tool reports Q, its complement Q̅, the previous state, the next state, the selected operation and whether the requested input combination is valid.

How to Use the SR Flip-Flop Simulator

Choose the initial stored Q state, then set S and R. Press Trigger Rising Clock Edge to sample the inputs and update the stored state.

Initial state:
Q = 0

Inputs:
S = 1
R = 0

Rising clock edge:
↑

Operation:
SET

Next state:
Q = 1
Q̅ = 0

After the pulse, the new Q becomes the stored state used by the next simulation step.

What Is an SR Flip-Flop?

SR stands for Set and Reset. The circuit stores one binary state and normally provides two complementary outputs, Q and Q̅.

The Set input requests Q=1, while Reset requests Q=0. When neither function is requested, the stored state is retained.

S = Set
R = Reset

Q  = stored output
Q̅ = complement of Q

SR Flip-Flop Truth Table

For the active-high model used by this simulator, the fundamental state table is:

S	R	Previous Q	Next Q	Operation
0	0	0	0	Hold
0	0	1	1	Hold
0	1	X	0	Reset
1	0	X	1	Set
1	1	X	Invalid	Forbidden

SR Flip-Flop Hold Condition

When both S and R are zero, neither set nor reset is requested. The flip-flop therefore retains the state stored before the active clock edge.

S = 0
R = 0

Previous Q = 0
Next Q = 0

Previous Q = 1
Next Q = 1

Operation:
HOLD

This ability to preserve a previous value is what makes the SR flip-flop a memory element rather than an ordinary logic gate.

SR Flip-Flop Set Condition

When S is one and R is zero, the active clock edge stores a logic one.

S = 1
R = 0

Previous Q:
0 or 1

After clock:
Q = 1
Q̅ = 0

Operation:
SET

If Q was already one, the stored value remains one, but the logical operation is still classified as Set.

SR Flip-Flop Reset Condition

When S is zero and R is one, the next stored state becomes zero.

S = 0
R = 1

Previous Q:
0 or 1

After clock:
Q = 0
Q̅ = 1

Operation:
RESET

Why S = 1 and R = 1 Is Invalid

For the conventional active-high SR structure, simultaneously asserting Set and Reset requests contradictory states. Set asks Q to become one while Reset asks Q to become zero.

S = 1
R = 1

SET request:
Q = 1

RESET request:
Q = 0

Both requests occur together.

Result:
Forbidden / Invalid

Because this combination does not represent a valid complementary stored state, the simulator flags it instead of inventing a next Q value.

SR Flip-Flop Q and Q̅ Outputs

During valid operation, Q and Q̅ are complements.

If:
Q = 0

Then:
Q̅ = 1


If:
Q = 1

Then:
Q̅ = 0

The complement relationship is intentionally not reported as a valid state for the forbidden S=R=1 input condition.

Previous State and Next State

Sequential circuits are usually described using present-state and next-state notation. Q(t) represents the value already stored, while Q(t+1) represents the state after the next active clock event.

Q(t):
Present stored state

Inputs:
S, R

Clock:
↑

Q(t+1):
New stored state

For the Hold condition, Q(t+1)=Q(t). Set and Reset instead force a specific next state.

SR Flip-Flop Characteristic Table

S	R	Q(t)	Q(t+1)
0	0	0	0
0	0	1	1
0	1	0	0
0	1	1	0
1	0	0	1
1	0	1	1
1	1	X	Invalid

SR Flip-Flop Characteristic Equation

For valid SR input combinations, a commonly used characteristic relationship is:

Q(t+1) =
S OR (Q(t) AND NOT R)

Constraint:

S AND R ≠ 1

The constraint is essential because the algebraic expression alone should not be used to define the forbidden S=R=1 state as valid.

SR Flip-Flop Excitation Table

An excitation table works in the opposite direction. Instead of asking what next state results from S and R, it asks which S and R values can produce a desired state transition.

Current Q	Desired Q Next	S	R
0	0	0	X
0	1	1	0
1	0	0	1
1	1	X	0

X indicates that more than one permissible input choice can produce the desired transition.

SR Flip-Flop Clock Operation

The simulator models a rising-edge-triggered SR flip-flop. S and R are sampled when the clock changes from low to high.

Before edge:
S = 1
R = 0
Q = 0

Clock:
0 → 1

After edge:
Q = 1

Changing an input in this ideal simulator does not alter the stored Q until a pulse is triggered.

SR Latch vs SR Flip-Flop

The terms latch and flip-flop are sometimes used loosely, but they describe different timing behavior.

Feature	SR Latch	SR Flip-Flop
Control	Level sensitive	Edge triggered
State changes	While enabled/input-active	At active clock edge
Memory	Yes	Yes
Set/Reset concept	Yes	Yes

This page intentionally simulates clock-edge behavior so it remains focused on an SR flip-flop rather than a continuously responsive SR latch.

NOR SR Latch and Active-High Logic

The familiar NOR-gate SR latch uses active-high Set and Reset inputs. That means logic 1 asserts the corresponding control.

Active-high convention:

S=1 → Set requested
R=1 → Reset requested

S=0,R=0 → Hold
S=1,R=1 → Forbidden

The logical state rules used by this simulator follow that familiar active-high convention, with state updates applied at the simulated rising clock edge.

NAND SR Latch vs Active-High SR

An SR latch implemented from NAND gates commonly uses active-low inputs, often written S̅ and R̅. Its input meanings therefore differ from the active-high convention used here.

Active-high SR:
S=1 → Set
R=1 → Reset

Typical active-low NAND SR:
S̅=0 → Set
R̅=0 → Reset

When comparing a truth table with a hardware circuit, always confirm whether the inputs are active-high or active-low.

SR Flip-Flop State Transition Example

Initial:
Q = 0

Pulse 1:
S=1 R=0
Q → 1
SET

Pulse 2:
S=0 R=0
Q → 1
HOLD

Pulse 3:
S=0 R=1
Q → 0
RESET

Pulse 4:
S=0 R=0
Q → 0
HOLD

The history table in the simulator records this type of sequence so you can follow the stored value across several clock cycles.

Why SR Flip-Flops Store One Bit

Q has only two valid stable values, zero and one. That makes the circuit capable of storing one binary bit.

Q = 0
stores binary 0

Q = 1
stores binary 1

Larger registers are constructed from multiple state-storage elements operating together.

SR Flip-Flop Applications

SR storage concepts are useful in control logic, state retention, switching circuits, event flags and the construction of more advanced sequential logic elements.

SR behavior also provides a useful foundation for understanding D, JK and T flip-flops because those circuits can be viewed as ways to control or extend basic set/reset storage behavior.

SR Flip-Flop vs D Flip-Flop

Feature	SR Flip-Flop	D Flip-Flop
Main data controls	S and R	D
Hold input combination	S=0,R=0	Depends on D/current edge
Forbidden S/R combination	Yes	No equivalent D-input conflict
Stores one bit	Yes	Yes

A D flip-flop is often easier to use for ordinary data storage because a single data input removes the conflicting Set/Reset combination.

SR Flip-Flop vs JK Flip-Flop

The JK flip-flop extends the SR concept so the input combination corresponding to both controls being asserted has defined behavior instead of being forbidden.

SR:
S=1,R=1 → Invalid

JK:
J=1,K=1 → Toggle

That defined toggle state is one of the important differences between the two flip-flop types.

Common SR Flip-Flop Mistakes

One common mistake is assuming that S=R=0 resets the circuit. In an active-high SR device, 00 is the Hold state, so the previous Q is preserved.

Another mistake is treating S=R=1 as a normal state. For the conventional active-high SR model it is forbidden and should not be used to define a reliable next state.

It is also important to distinguish a clocked flip-flop from an SR latch. An edge-triggered flip-flop changes stored state at its active clock edge, while a latch is level sensitive.

SR Flip-Flop Simulator Limitations and Notes

This simulator models an ideal active-high SR flip-flop with a rising clock edge. It does not model physical propagation delay, setup time, hold time, metastability or electrical voltage levels.

The forbidden S=R=1 condition is reported as invalid rather than predicting a hardware-specific resulting state. Real circuits leaving a forbidden condition can depend on gate delays and physical implementation.

Q and Q̅ are shown as logical complements only for valid stored states. The simulator’s clock history exists only for the current page session and resets when the simulator is reset or the page is reloaded.

SR Flip-Flop Simulator FAQs

What is an SR flip-flop?

An SR flip-flop is a one-bit sequential storage element controlled by Set and Reset inputs.

What does S mean in an SR flip-flop?

S means Set. In this active-high model, S=1 with R=0 sets Q to 1 at the active clock edge.

What does R mean?

R means Reset. R=1 with S=0 causes Q to become 0 at the active edge.

What happens when S=0 and R=0?

The flip-flop holds its previous Q state.

What happens when S=1 and R=0?

The Set operation occurs and Q becomes 1.

What happens when S=0 and R=1?

The Reset operation occurs and Q becomes 0.

What happens when S=1 and R=1?

That is the forbidden input condition for the active-high SR model and the simulator reports it as invalid.

What is Q̅?

Q̅ is the complement of Q during valid operation. If Q=1, Q̅=0, and if Q=0, Q̅=1.

What does Hold mean?

Hold means the next Q state remains equal to the previously stored Q state.

Does changing S or R immediately change Q?

Not in this simulator. Inputs are sampled when you trigger the rising clock edge.

What is the SR flip-flop characteristic equation?

For valid input states, Q(t+1)=S OR (Q(t) AND NOT R), subject to the constraint that S and R are not both 1.

What is the difference between an SR latch and SR flip-flop?

An SR latch is level sensitive, while the model simulated here updates state on a clock edge.

Why is S=R=1 forbidden?

Set and Reset request opposing stored states simultaneously, so the normal complementary Q/Q̅ relationship cannot be defined reliably.

How many bits does an SR flip-flop store?

It stores one binary bit.

What is the difference between SR and JK flip-flops?

The JK flip-flop defines the J=K=1 condition as Toggle, while the corresponding S=R=1 condition is forbidden in the basic SR model.

Does this simulator model setup and hold time?

No. It models ideal logical state transitions rather than physical timing characteristics.