JK Flip-Flop Simulator
Simulate a rising-edge JK flip-flop and track its stored state across successive clock pulses. Set J and K, initialize Q, preview the next state and test Hold, Set, Reset and Toggle operations with Q and Q̅.
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FLIP-FLOP Rising Edge
| Pulse | J | K | Previous Q | Next Q | Q̅ | Operation |
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JK Flip-Flop Simulator
The JK Flip-Flop Simulator demonstrates the state transitions of a clocked JK flip-flop. A JK flip-flop is a sequential logic element that stores one binary bit and updates its Q output according to the J and K inputs at an active clock edge.
The JK flip-flop extends the basic SR concept by defining a useful operation for the condition where both control inputs are high. Instead of producing a forbidden state, J=1 and K=1 causes the stored output to toggle.
This simulator uses an ideal active-high, rising-edge-triggered model. Each clock pulse updates the stored Q value, so you can simulate a sequence of states instead of evaluating each input combination independently.
How to Use the JK Flip-Flop Simulator
Choose an initial Q state, then set J and K. Press Evaluate Next State to preview what would happen at the next rising clock edge, or press Trigger Rising Clock Edge to actually update the stored state.
Initial state:
Q = 0
J = 1
K = 0
Clock:
↑
Operation:
SET
Next state:
Q = 1
Q̅ = 0The new Q then becomes the previous state for the next clock pulse.
What Is a JK Flip-Flop?
A JK flip-flop is a bistable sequential logic circuit with two primary control inputs named J and K. It stores one binary state represented by Q and normally provides its complement Q̅ as a second output.
J = control input
K = control input
Q = stored output
Q̅ = complement of QIts four input combinations correspond to Hold, Reset, Set and Toggle operations.
JK Flip-Flop Truth Table
| J | K | Previous Q | Next Q | Operation |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | Hold |
| 0 | 0 | 1 | 1 | Hold |
| 0 | 1 | X | 0 | Reset |
| 1 | 0 | X | 1 | Set |
| 1 | 1 | 0 | 1 | Toggle |
| 1 | 1 | 1 | 0 | Toggle |
JK Flip-Flop Hold Condition
When J=0 and K=0, the flip-flop does not request a change. The next state remains equal to the previous state.
J = 0
K = 0
If Q(t) = 0:
Q(t+1) = 0
If Q(t) = 1:
Q(t+1) = 1
Operation:
HOLDJK Flip-Flop Set Condition
When J=1 and K=0, the next state becomes one regardless of the previous Q.
J = 1
K = 0
Q(t) = 0 → Q(t+1) = 1
Q(t) = 1 → Q(t+1) = 1
Operation:
SETJK Flip-Flop Reset Condition
When J=0 and K=1, the next stored state becomes zero.
J = 0
K = 1
Q(t) = 0 → Q(t+1) = 0
Q(t) = 1 → Q(t+1) = 0
Operation:
RESETJK Flip-Flop Toggle Condition
The distinctive JK operation occurs when both J and K are one. The stored state changes to its complement on each active clock edge.
J = 1
K = 1
If:
Q(t) = 0
Then:
Q(t+1) = 1
If:
Q(t) = 1
Then:
Q(t+1) = 0
Operation:
TOGGLEThis valid toggle behavior is one of the main differences between JK and the basic SR flip-flop.
JK Flip-Flop State Table
| J | K | Meaning | Next-State Rule |
|---|---|---|---|
| 0 | 0 | Hold | Q(t+1)=Q(t) |
| 0 | 1 | Reset | Q(t+1)=0 |
| 1 | 0 | Set | Q(t+1)=1 |
| 1 | 1 | Toggle | Q(t+1)=NOT Q(t) |
JK Flip-Flop Characteristic Equation
The next-state behavior can be represented by the characteristic equation:
Q(t+1) =
J·Q̅(t) + K̅·Q(t)
Equivalent word form:
Q(t+1) =
(J AND NOT Q(t))
OR
(NOT K AND Q(t))This equation correctly represents Hold, Set, Reset and Toggle operations.
Checking the JK Characteristic Equation
Consider J=1, K=1 and Q(t)=0.
Q(t+1) =
(J AND NOT Q)
OR
(NOT K AND Q)
J = 1
K = 1
Q = 0
NOT Q = 1
NOT K = 0
Q(t+1) =
(1 AND 1)
OR
(0 AND 0)
= 1 OR 0
= 1Because Q was zero, the toggle operation changes it to one.
JK Flip-Flop Excitation Table
An excitation table specifies suitable J and K values for moving from a known current state to a desired next state.
| Current Q | Next Q | J | K |
|---|---|---|---|
| 0 | 0 | 0 | X |
| 0 | 1 | 1 | X |
| 1 | 0 | X | 1 |
| 1 | 1 | X | 0 |
X means either zero or one may be used without preventing the desired transition.
JK Flip-Flop Clock Operation
This simulator uses rising-edge operation. J and K are sampled when the clock transitions from low to high.
Before edge:
J = 1
K = 1
Q = 0
Clock:
0 → 1
After edge:
Q = 1Changing J or K without triggering the simulated clock does not modify the stored Q.
JK Flip-Flop Toggle Sequence
If J and K remain high for several rising edges, the output alternates between zero and one.
Initial Q = 0
J = 1
K = 1
Pulse 1:
Q = 1
Pulse 2:
Q = 0
Pulse 3:
Q = 1
Pulse 4:
Q = 0This repeated toggle behavior is useful when studying frequency division and binary counters.
JK Flip-Flop as a Toggle Flip-Flop
Connecting J and K permanently to logic one causes the JK device to toggle on every active clock edge.
J = 1
K = 1
Each rising edge:
Q(next) = NOT Q(current)Under ideal edge-triggered operation, this makes the Q output change state once per active input clock edge and can be used as a divide-by-two stage when interpreted as a periodic waveform.
JK Flip-Flop Frequency Division
When J=K=1 continuously, Q alternates state on each rising edge. A full Q cycle requires two input clock edges, so the output repetition rate is one-half the input clock repetition rate in the ideal toggle configuration.
Clock edges:
1 2 3 4 5 6
Q:
1 0 1 0 1 0
Output frequency:
approximately CLK / 2JK Flip-Flop in Binary Counters
The toggle behavior makes JK flip-flops useful for understanding binary counter design. Multiple stages can be arranged so different bits change according to clock and control conditions.
Conceptual binary counting:
000
001
010
011
100
101
110
111Actual synchronous and asynchronous counter circuits use specific clock and gating arrangements, but the JK toggle function is a common building block.
JK Flip-Flop vs SR Flip-Flop
| Inputs | SR Flip-Flop | JK Flip-Flop |
|---|---|---|
| 00 | Hold | Hold |
| 01 | Reset | Reset |
| 10 | Set | Set |
| 11 | Forbidden | Toggle |
The removal of the forbidden 11 state is the defining practical improvement of the JK state table over the basic SR state table.
Why JK Has No Forbidden 11 State
The JK feedback structure defines the J=K=1 combination as a request to invert the current state instead of simultaneously forcing Q both high and low.
SR:
S=1,R=1
→ forbidden
JK:
J=1,K=1
→ Q(next)=NOT Q(current)The previous Q value therefore determines the result of the 11 input combination.
JK Flip-Flop vs D Flip-Flop
| Feature | JK Flip-Flop | D Flip-Flop |
|---|---|---|
| Data/control inputs | J and K | D |
| Toggle operation | Built in with J=K=1 | Requires feedback logic |
| Next state | Depends on J,K,Q | Normally follows D at edge |
| Stores one bit | Yes | Yes |
JK Flip-Flop vs T Flip-Flop
A T flip-flop focuses specifically on Hold and Toggle behavior. A JK flip-flop can reproduce that behavior by tying J and K together.
Connect:
J = T
K = T
Then:
T = 0
J=0,K=0
→ Hold
T = 1
J=1,K=1
→ TogglePrevious State and Next State
Because the JK flip-flop is sequential, the previous stored value is essential when evaluating some input combinations.
J=1,K=1
If previous Q = 0:
next Q = 1
If previous Q = 1:
next Q = 0A truth table that omits the previous state cannot completely describe the toggle operation.
Q and Q̅ Outputs
For normal ideal JK operation, Q and Q̅ remain complementary.
Q = 0
Q̅ = 1
Q = 1
Q̅ = 0When the flip-flop toggles, both logical outputs reverse together.
Race-Around Condition in JK Flip-Flops
The race-around condition is associated with certain level-triggered JK implementations when J=K=1 and the clock remains active long enough for the state to change repeatedly within one clock interval.
Edge-triggered or master-slave implementations are used to control that behavior. This simulator intentionally uses one discrete state change per rising clock edge and therefore does not model race-around timing.
This simulator:
one rising edge
→ one state evaluation
→ at most one toggleMaster-Slave JK Flip-Flop
A master-slave JK structure uses two storage stages controlled by opposite clock phases so that input sampling and output updating occur in separate phases.
The approach historically helped control repeated switching during an active clock interval. The simulator does not attempt to model the internal master and slave timing stages; it models the resulting edge-based logical behavior.
JK Flip-Flop State Transition Example
Initial:
Q = 0
Pulse 1:
J=1 K=0
SET
Q = 1
Pulse 2:
J=0 K=0
HOLD
Q = 1
Pulse 3:
J=1 K=1
TOGGLE
Q = 0
Pulse 4:
J=1 K=1
TOGGLE
Q = 1
Pulse 5:
J=0 K=1
RESET
Q = 0The simulator’s history table makes sequences like this easy to test.
JK Flip-Flop Applications
JK flip-flops are useful for learning and implementing state storage, toggle operations, counters, frequency division and sequential control logic.
The flexible Hold, Set, Reset and Toggle operations make the JK state table particularly useful for understanding how sequential circuits move between binary states.
Common JK Flip-Flop Mistakes
A common mistake is treating J=K=1 as invalid because that combination is forbidden in a basic SR flip-flop. In a JK flip-flop, 11 is specifically the Toggle state.
Another mistake is assuming toggle always means Q becomes one. Toggle means inversion: zero becomes one and one becomes zero.
It is also important to include the previous Q state when evaluating J=K=0 or J=K=1 because both operations depend directly on the stored state.
JK Flip-Flop Simulator Limitations and Notes
This tool models an ideal active-high, rising-edge-triggered JK flip-flop. It does not simulate physical propagation delay, setup time, hold time, metastability, clock skew or voltage thresholds.
Each simulated rising edge causes at most one state transition. The simulator therefore does not reproduce race-around behavior associated with some level-triggered JK circuits.
The state history is maintained only while the current page session is active. Resetting the simulator or reloading the page starts a new sequence.