Cache Address Breakdown

Cache Tag Index Offset Calculator

Split a memory address into its cache tag, set index, and block offset. Enter cache geometry and address width to see the exact field values, bit counts, binary representation, and cache-set mapping.

Tag bits Index bits Offset bits

Split Address into Tag | Index | Offset

Memory address Byte address

Format

Address width

Cache size Bytes

Cache line size Bytes

Associativity Ways

Example: 32 KiB cache, 64-byte lines, 8-way associativity → 64 sets, 6 index bits, 6 offset bits.

Cache Tag 0x12 18 decimal

Set Index 13 Set 13 of 64

Block Offset 5 5 bytes into line

Tag Bits 00000000000000010010

Index Bits 001101

Offset Bits 000101

Tag Width 20 bits

Index Width 6 bits

Offset Width 6 bits

Cache Sets 64

Address decomposition

32-bit address = 20 tag bits | 6 index bits | 6 offset bits

Cache Address Fields

What Are Cache Tag, Index, and Offset Bits?

In a conventional set-associative cache, a memory address is separated into three logical regions: the cache tag, set index, and block offset. Each field has a different job during cache lookup.

The lowest address bits form the block offset and select a byte inside a cache line. The next group of bits forms the set index and selects one cache set. The remaining higher-order bits become the tag.

Address layout Memory Address = Tag | Set Index | Block Offset

How to Use

How to Use the Cache Tag Index Offset Calculator

Enter the memory address Use hexadecimal or decimal notation and select the matching input format.

Select the address width Choose the logical width of the address, such as 32 or 64 bits. Auto uses the minimum number of bits needed to represent the supplied address.

Enter the cache geometry Provide cache capacity, cache-line size, and associativity in ways.

Read the field breakdown The calculator returns the tag, set index, block offset, field widths, cache set count, and binary value of every field.

Cache Geometry

How to Calculate the Number of Cache Sets

Before the index field can be extracted, the number of sets in the cache must be known. Cache capacity is divided by cache-line size to determine the total number of lines, and those lines are divided among the available ways.

Total cache lines totalLines = cacheSize / lineSize

Number of sets sets = cacheSize / (lineSize × associativity)

For a 32 KiB cache with 64-byte lines and 8-way associativity, there are 512 total lines and 64 sets.

Worked Example

32-Bit Address 0x12345 in a 32 KiB 8-Way Cache

Consider address 0x12345, a 32 KiB cache, 64-byte cache lines, 8-way associativity, and a 32-bit address width.

Complete cache field calculation

Address = 0x12345 Address width = 32 bits Cache size = 32768 bytes Line size = 64 bytes Associativity = 8 Total lines: 32768 / 64 = 512 Cache sets: 512 / 8 = 64 Offset bits: log2(64) = 6 Index bits: log2(64) = 6 Tag bits: 32 – 6 – 6 = 20 Block offset: 0x12345 mod 64 = 5 Line number: floor(0x12345 / 64) = 1165 Set index: 1165 mod 64 = 13 Tag: floor(1165 / 64) = 18 = 0x12

Offset Field

How to Calculate Cache Block Offset Bits

The block offset selects a byte within a cache line. When line size is a power of two, the number of offset bits is simply the base-2 logarithm of that line size.

Offset width offsetBits = log₂(lineSize)

A 64-byte line needs 6 offset bits because 64 = 2⁶. Its valid byte offsets therefore range from 0 through 63.

Line Size	Power of Two	Offset Bits	Offset Range
16 bytes	2⁴	4	0–15
32 bytes	2⁵	5	0–31
64 bytes	2⁶	6	0–63
128 bytes	2⁷	7	0–127
256 bytes	2⁸	8	0–255

Index Field

How to Calculate Cache Index Bits

The index field selects one set from all available cache sets. If the cache contains a power-of-two number of sets, its required index width is the base-2 logarithm of the set count.

Index width indexBits = log₂(numberOfSets)

A cache containing 64 sets requires 6 index bits. A cache containing 256 sets requires 8 index bits.

Tag Field

How Many Cache Tag Bits Are Required?

Once the offset and index widths are known, the remaining upper address bits form the tag field.

Tag width tagBits = addressWidth – indexBits – offsetBits

For a 32-bit address using 6 index bits and 6 offset bits, 20 bits remain for the tag.

32-bit field layout

Address width = 32 bits Tag bits = 20 Index bits = 6 Offset bits = 6 20 + 6 + 6 = 32 Address: +———————-+——–+——–+ | TAG 20 | IDX 6 | OFF 6 | +———————-+——–+——–+

Extract Values

Tag, Index, and Offset Value Formulas

Field widths describe how many bits each section occupies, while field values tell you the actual tag, set, and byte position for a specific address.

Block offset offset = address mod lineSize

Set index index = floor(address / lineSize) mod numberOfSets

Cache tag tag = floor(address / (lineSize × numberOfSets))

Bitwise Extraction

Extract Cache Fields with Masks and Shifts

When the cache line size and set count are powers of two, the same values can be obtained using shifts and masks.

Generic bitwise form

offsetMask = lineSize – 1 indexMask = numberOfSets – 1 offset = address & offsetMask index = (address >> offsetBits) & indexMask tag = address >> (offsetBits + indexBits)

This matches the way conventional hardware cache address fields are often described in computer architecture exercises.

Address Width

Why Address Width Matters for Tag Bits

The numerical tag value can be found from the address regardless of how many leading zero bits are displayed. The number of tag bits, however, depends on the logical address width.

For example, the same small address may have 20 tag bits in a 32-bit address format but 52 tag bits in a 64-bit format when index and offset consume a combined 12 bits.

Use the address width expected by your architecture or exercise. The Auto setting uses only the minimum number of bits needed to represent the supplied address, so it is useful for mathematical decomposition but may not match a processor’s full architectural address width.

Associativity

How Associativity Changes the Index and Tag Fields

For a fixed cache capacity and line size, increasing associativity reduces the number of cache sets. Fewer sets require fewer index bits, leaving more high-order address bits for the tag.

32 KiB Cache	Line Size	Associativity	Sets	Index Bits
32 KiB	64 B	1-way	512	9
32 KiB	64 B	2-way	256	8
32 KiB	64 B	4-way	128	7
32 KiB	64 B	8-way	64	6
32 KiB	64 B	16-way	32	5

Direct Mapped

Tag Index Offset for a Direct-Mapped Cache

A direct-mapped cache is simply a one-way cache. Every set holds exactly one line, so the number of sets equals the total number of cache lines.

For a 32 KiB direct-mapped cache with 64-byte lines, there are 32768 / 64 = 512 sets. This requires 9 index bits.

A 32-bit address in that cache therefore uses 6 offset bits, 9 index bits, and 17 tag bits.

Fully Associative

What Happens in a Fully Associative Cache?

A fully associative cache has only one set containing every cache line. Since there is just one set, no address bits are needed to select among sets.

Fully associative cache numberOfSets = 1 → indexBits = 0

The address is then divided only into a tag and a block offset.

Same Set

Why Different Addresses Can Have the Same Index

Only the index bits select the cache set. Multiple addresses can therefore contain the same index bits while having different tag bits.

Those addresses compete for the ways of the same set. If too many active memory blocks map to one set, conflict misses can occur.

Example with 64 sets

Line number 13: 13 mod 64 = index 13 Line number 77: 77 mod 64 = index 13 Line number 141: 141 mod 64 = index 13 Same index Different tags

Common Geometries

Example Tag Index Offset Bit Counts

Address Width	Cache	Line	Ways	Tag	Index	Offset
32 bits	32 KiB	64 B	8	20	6	6
32 bits	32 KiB	64 B	4	19	7	6
32 bits	16 KiB	32 B	4	20	7	5
32 bits	64 KiB	64 B	8	19	7	6
64 bits	32 KiB	64 B	8	52	6	6

Applications

Where Tag Index Offset Calculations Are Useful

Computer Architecture

Solve exercises that require splitting memory addresses into cache fields.

Cache Design

Study how capacity, line size, and associativity determine address-field width.

Performance Analysis

Understand why particular memory addresses map to the same cache set.

Systems Programming

Reason about cache-line placement and low-level memory-access patterns.

Embedded Systems

Analyze known cache geometries on processors with specific address widths.

Education

Verify hand calculations for tags, index fields, block offsets, and set counts.

Model Limits

Conventional Cache Mapping vs Real Processor Details

This calculator models the standard power-of-two cache organization taught in computer architecture: fixed line size, fixed set count, and ordinary tag/index/offset decomposition from a byte address.

Some real processors use additional functions such as virtual indexing, physical tagging, address hashing, cache slices, XOR-based indexing, or other implementation-specific transformations.

For processor-specific cache reverse engineering, always verify whether the target cache actually uses the simple bit-field mapping modeled here.

Common Mistakes

Common Tag Index Offset Calculation Mistakes

Using cache capacity directly for the index

The index depends on the number of sets, not directly on the total number of bytes in the cache.

Ignoring associativity

Associativity changes the number of sets and therefore changes both index width and tag width.

Confusing line offset with set index

Offset bits identify a byte inside a line. Index bits identify a cache set.

Forgetting the address width

The tag value may remain numerically the same, but the number of leading tag bits depends on the logical address width.

Counting line size in bits instead of bytes

Cache line size in these formulas is measured in addressable bytes.

Assuming every real cache uses direct bit selection

Some microarchitectures use hashing or other functions that modify the conventional mapping.

FAQ

Cache Tag Index Offset Calculator FAQs

Calculate the offset width from cache-line size, calculate the index width from the number of sets, and assign the remaining high address bits to the tag.

For a power-of-two line size, offset bits equal log2 of the cache-line size in bytes.

First calculate the number of sets, then take log2 of that set count.

Subtract index bits and offset bits from the selected logical address width.

Six bits, because 64 bytes equals 2^6.

For a 32 KiB cache, 64-byte lines, 8-way associativity, and a 32-bit address, the tag value is 0x12.

The set index is 13 because the cache has 64 sets and memory line number 1165 maps to set 13.

There is only one set, so the index width is zero bits. The address contains only tag and block-offset fields.

Enter 1. A direct-mapped cache is equivalent to one-way associativity.

Offset and index widths are determined by cache geometry. Any remaining bits from the full logical address width belong to the tag.

Yes. Select Hexadecimal and enter a value such as 0x12345 or 0xABCDEF.

No. It models conventional power-of-two tag/index/offset cache mapping. Some processors use additional hashing, virtual indexing, or cache-slice functions.